SGMII and Gb Ethernet PCS IP Core

Bridging and PHY Implementations

This IP has reached End of Life (EOL) and is now archived. It has been merged with the Tri-Speed Ethernet IP Core. The last update for this IP was in release 2024.2 (v1.7.1), and any newer updates will now be reflected under the latest Tri-Speed Ethernet IP Core. For migration guidelines, please refer to the IP EOL Product Bulletin.

Jump to

Block Diagram

Documentation

Quick Reference
Technical Resources
Information Resources
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
LatticeECP3 and Broadcom 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN12171.07/26/2010PDF1.5 MB
SGMII and Gb Ethernet PCS IP User Guide
FPGA-IPUG-020772.012/20/2024PDF1.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
LatticeECP3 and Broadcom 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN12171.07/26/2010PDF1.5 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

TITLENUMBERVERSIONDATEFORMATSIZE
Select All
LatticeECP3 and ECP5 SGMII and Gb Ethernet PCS IP Core User Guide
IPUG1161.011/24/2014PDF4.2 MB
SGMII and Gb Ethernet PCS IP Core User Guide
IPUG602.14/1/2014PDF3.6 MB
SGMII and Gb Ethernet PCS IP User Guide
FPGA-IPUG-020772.012/20/2024PDF1.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Product Bulletin - IP End-of-Life (EOL) Notice 1H 2025
FPGA-PB-020231.011/24/2025PDF222.6 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
SGMII and Gb Ethernet PCS IP Release Notes
FPGA-RN-020351.012/20/2024PDF213.5 KB