The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core: Rotation, Translation, Sin and Cos, Arctan. Two architecture configurations are available for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial, with multiple cycles throughput. The input data, output data widths and iterative number are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for rounding.
Latest Resource Utilization details are available in the IP Core User Guide.
Features
- Functions supported:
- Vector rotation (polar to rectangular)
- Vector translation (rectangular to polar)
- Sin and cos
- Arctan
- Input data widths from 8 to 32 bits
- Optional amplitude compensation scaling module to compensate for CORDIC algorithm’s output amplitude scale factor
- Selectable rounding : Truncation, Rounding Up, Rounding away from zero, Convergent Rounding
- Parallel architectural configuration for high throughput
