GPIO IP核

存储器映射IO或APB IO控制

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通用输入/输出（GPIO）外设IP旨在通过莱迪思存储器映射接口（LMMI）或高级外设总线接口（APB）来控制GPIO。配置为输入端口时，它可以通过读取相关寄存器的状态来检测某一GPIO的状态。配置为输出端口时，它取出写入相关寄存器的值并控制受控GPIO的状态。

该IP可以连接到CPU总线，也可以在需要I/O内存组织的桥接/外围设备中使用。IP生成器可根据GPIO的数量进行配置，以灵活使用GPIO端口。

特性

通过单独的寄存器设置或清除输出，从而对输出并行控制
通过单个寄存器设置或清除输出
单独的输入和输出数据以及控制寄存器
输出寄存器反映输出驱动状态
输入寄存器反映输入状态
所有输入都可配置为INT源，具有可配置的边沿或电平检测
中断符合莱迪思中断接口（LINTR）

联系销售

Block Diagram

放大图片

GPIO Top Level Block Diagram

Resource Utilization

Nexus Family
LIFCL-40-9BG400I
Configuration	Clk Fmax (MHz)*	Registers	LUTs
Default	200	11	34
Number of I/O Lines is 32	200	361	345
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled	200	361	374

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFD2NX-40-9BG2561I
Configuration	Clk Fmax (MHz)*	Registers	LUTs
Default	200	20	35
Weighted Round robin	200	361	345
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled	200	361	374

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

LFCPNX-100-9LFG672I
Configuration	Clk Fmax (MHz)*	Registers	LUTs
Default	200	20	35
Weighted Round robin	200	361	345
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled	200	361	374

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

文档

快速参考

User Manual

资讯资源

Release Notes

下载

IP Cores

标题	编号	版本	日期	格式	文件大小
选择全部
GPIO IP Core - User Guide	FPGA-IPUG-02076	2.4	6/26/2025	PDF	600.7 KB

标题	编号	版本	日期	格式	文件大小
选择全部
GPIO IP Core - Release Notes	FPGA-RN-02026	1.2	6/26/2026	PDF	348.5 KB