The Lattice Semiconductor RISC-V SM CPU IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
Resource Utilization details are available in the IP Core User Guide.
Features
- RV32I instruction set
- Five stages of pipelines
- Support the AHB-L bus standard for instruction/data port
- Optional debug through Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)
- Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification Revision 1.10
