Lattice Semiconductor general-purpose I2C Target IP provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides you with the flexibility of configuring the I2C Target device to any legal Target address, thus, avoiding a potential Target address collision on an I2C bus with multiple Target devices.
Latest Resource Utilization details are available in the IP Core User Guide.
Features
- Supports 7-bit and 10-bit Addressing Mode.
- Supports the following bus speeds:
- Standard-mode (Sm) – up to 100 kbit/s
- Fast-mode (Fm) – up to 400 kbit/s
- Fast-mode Plus (Fm+) – up to 1 Mbit/s
- Supports Clock stretching
- Programmable ACK/NACK response on address and data phases
- Integrated pull-up through FPGA I/O settings
