The AXI Register Slice core connects one AXI standard manager to one AXI standard subordinate by introducing pipeline stages in between the two to close timing in critical paths. Different configuration options are available. Each AXI channel transfers information in only one direction and the architecture does not require a fixed relationship between the channels. The user can insert a register slice at almost any point in any channel, with an additional cycle of latency.
Resource Utilization details are available in the IP Core User Guide.
Features
- Individually configurable AXI channels.
- One latency cycle per register-slice by default.
- Support for AXI3, AXI4, and AXI4-Lite modes of the AXI protocol.
- Full-Weight, Light-Weight, and Input Registered modes of operation.
- Ability to facilitate timing closure by trading-off frequency versus latency.
