FIFO Interface – To transfer data over non-zero endpoint, user just needs to manage this FIFO interface. User can write down VHDL, Verilog or System Verilog code to manage this FIFO interface.
Software managed control endpoint - In this IP core, processor is responsible to manage transfer for endpoint 0 (default control endpoint). IP core has AHB Lite interface by which processor can communicate with IP core. This provides flexibility to the user to manage enumeration data.
Application - This IP core is well suited when user recognizes that software is not required to process data to be passed over data endpoint.
Features
- Supports LS (1.5 Mbps), FS (12 Mbps) and HS (480 Mbps) modes
- Supports Control, Bulk, Interrupt and Isochronous transfers
- Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints)
- Supports Test modes (Test J, Test K, Test SE0 NAK, Test Packet)
- Ready to use component
