What’s New in Propel 2026.1
Discover what’s new in Lattice Propel 2026.1, featuring enhancements that improve user experience and streamline intuitive design creation. Watch now to see how the latest updates help you build FPGA-based embedded systems faster and focus on innovation.
Date: June 26, 2026 (English) Watch Now
What’s New in Radiant 2026.1
Lattice Radiant 2026.1 is purpose-built to help designers maximize productivity for small and mid-range FPGA designs. This release turbocharges development speed and drives unparalleled usability.
Date: June 26, 2026 (English) Watch Now
FPGA‑accelerated 3D Sensing for Humanoid Robot Manipulation
This demo showcases a miniaturized 3D sensor module built on AIRY3D’s patented TDM technology, mounted on a humanoid robotic arm and interfaced with the Lattice CrossLink™-NX 40 FPGA. The FPGA offloads the majority of depth computation, reducing system load and enabling efficient operation alongside an application processor such as the NVIDIA Jetson Orin™ Nano. With a wide field of view and no occlusion, the sensor delivers accurate near‑field depth awareness. This capability opens new opportunities for robotic grasping, in‑hand manipulation, and end‑effector‑mounted perception, supporting more responsive and intelligent humanoid robotics systems.
Multi‑sensor 10GbE Aggregation for NVIDIA Holoscan Using Lattice FPGAs
This demo highlights the DA322 Holoscan Adapter from Tauro Technologies, a compact multi‑sensor aggregation platform built on a low power Lattice CertusPro™‑NX FPGA. The solution supports four MIPI CSI‑2 camera inputs and aggregates HDMI, MIPI, or GMSL data into a single 10 GbE stream for efficient sensor ingest. Using RDMA, the platform feeds synchronized, high‑bandwidth data directly into NVIDIA Orin™ or Thor™ systems for real‑time visualization. With Precision Time Protocol (IEEE 1588‑2019), flexible multi‑function I/O, and an SFP+ 10 Gbps interface, the design enables scalable, space‑efficient sensor integration for advanced edge AI and visualization applications.
Real‑time 4K30 Embedded Vision Pipeline on Lattice Avant™ FPGAs
This demo showcases a real‑time 4K30 imaging pipeline implemented on the Lattice Avant FPGA platform, highlighting a complete embedded vision workflow from sensor input through FPGA‑based ISP processing to low‑latency HDMI output. The design demonstrates how Lattice Avant enables high‑performance, modular image signal processing that can be adapted to application‑specific requirements while maintaining real‑time operation. Designed for evaluation, rapid prototyping, and scalable camera development, the solution illustrates the flexibility and performance of Lattice Avant for next‑generation embedded vision systems.
Multi‑camera Aggregation for Real‑time Edge AI on Lattice Avant™ FPGAs
This demo showcases a scalable multi‑camera aggregation architecture using a Lattice Avant‑X FPGA and NVIDIA Hololink™ technology to enable ultra‑low‑latency sensor ingest for edge AI systems. Multiple camera streams are synchronized, aggregated, and preprocessed on the FPGA before being transmitted over standard 10 G or 25 G Ethernet to NVIDIA Thor™ for real‑time AI processing. By offloading camera handling, timestamping, and data conditioning from the host, the design reduces system overhead while delivering high‑bandwidth, deterministic performance. The demo highlights an AI‑ready pipeline optimized for demanding applications such as ADAS, robotics, aerospace, defense, and industrial vision.
SLVS‑EC 3.1 Image Sensor Interface on Lattice Avant™ FPGAs
This demo showcases an SLVS‑EC 3.1 image sensor interface implemented using Macnica’s SLVS‑EC IP on Lattice Avant-G and Avant-X FPGAs. Designed to support the latest Sony SLVS‑EC image sensors, the solution enables high‑performance, low‑power image capture in a compact FPGA footprint. The design supports backward compatibility with earlier SLVS‑EC standards, flexible pixel widths, multiple lane configurations, and ECC for secure data transmission. With built‑in features such as de‑skew and byte‑to‑pixel conversion, the demo highlights how Lattice Avant FPGAs simplify system design and accelerate evaluation of next‑generation high‑resolution imaging applications.
Aurora to 10G Ethernet Protocol Conversion on Lattice Avant™ FPGAs
This demo showcases an FPGA‑based protocol conversion solution from Lattice partner A.L.S.E that bridges Aurora high‑speed serial links to standard 10G Ethernet. Targeting imaging and data acquisition systems where Aurora is commonly used for low‑latency, high‑bandwidth data transfer, the design demonstrates a scalable alternative to custom PCIe boards for PC connectivity. Using a Lattice Avant Versa kit with dual SFP+ interfaces, the solution converts Aurora traffic to 10G Ethernet, simplifying system integration while maintaining performance and flexibility across heterogeneous protocols.
Single‑Chip EtherCAT® Motor Control on Lattice FPGAs
This demo showcases an integrated EtherCAT motor control solution implemented on a single Lattice FPGA, designed for real‑time motion control nodes in industrial automation systems. The design combines cyclic EtherCAT process data exchange with a deterministic field‑oriented control (FOC) motor control subsystem, delivering high‑dynamic performance with minimal latency. An embedded RISC‑V processor manages configuration and application control, while single‑chip integration consolidates EtherCAT communication, the FOC control loop, and encoder interfaces to reduce BOM, save board space, and improve system determinism.
Low Power PQC‑enabled FPGA and TPM Platform for Secure Physical AI
This demo showcases a joint Lattice, SEALSQ, and Promwad reference board designed to accelerate development of secure physical AI and industrial control systems. The platform combines a low power Lattice FPGA acting as a Root of Trust with a SEALSQ post‑quantum cryptography (PQC)‑compliant TPM, enabling secure boot, device attestation, and ongoing cyber‑resilient monitoring. With support for TPM 2.0 PQC extensions, anti‑tamper protection, and real‑time deterministic control, the reference design provides a practical foundation for building future‑ready systems that require strong security, flexibility, and rapid prototyping.
10BASE‑T1S Network Interoperability Demo on Lattice CertusPro™‑NX
This demo presents a 10BASE‑T1S Ethernet network evaluation platform developed with Canova Tech, showcasing throughput and interoperability across a mixed‑topology network. The design integrates Canova Tech’s 10BASE‑T1S Digital Controller IP synthesized on a Lattice CertusPro‑NX FPGA, with logic boards implementing MAC functionality, data handling, and control logic. A microcontroller manages system initialization, configuration, and MAC‑PHY interaction through standard interfaces, including OPEN Alliance and Media Independent Interface (MII). Together, the solution demonstrates a practical approach for validating 10BASE‑T1S Ethernet in automotive and industrial networking environments.
Full‑Bridge PCIe® Demo with NXP Hosts and Lattice Certus™ FPGAs
This demo highlights Lattice’s full‑bridge PCIe IP implemented on a Lattice Certus FPGA and demonstrated with NXP host processors. The FPGA appears as a standard PCIe endpoint with memory‑mapped BAR space, while also acting as a bus master capable of initiating transactions back to the host. A configurable application layer and embedded RISC‑V processor showcase mailbox‑based command handling, register access, and host‑to‑flash programming and verification over PCIe. By eliminating the need for an external bridge device, the design demonstrates how a single PCIe link enables efficient, bidirectional communication and remote update capabilities in NXP‑based systems.
Dual HPM Single SCM LTPI Demo
This demo showcases a high-performance LTPI setup using a single System Control Module (SCM) connected to two Host Processor Modules (HPMs) via the Lattice MachXO3™ device. It demonstrates efficient aggregation of low-speed signals—GPIO, UART, and I2C—from the SCM to both HPMs, with real-time link status monitoring and environmental sensing. Each LTPI link operates independently, ensuring uninterrupted CPLD functionality even if one HPM disconnects.
Lattice PQC Solution for Lattice MachXO5™-NX 55TDQ and PFR Demo
This demo highlights Lattice Semiconductor’s industry-first PQC-ready secure control FPGA, the Lattice MachXO5-NX 55TDQ, showcasing a single-chip solution that integrates attestation verifier, Platform Firmware Resiliency (PFR), and LTPI capabilities. Built on the power-efficient Lattice Nexus™ platform, the demo demonstrates robust post-quantum cryptography (PQC) support compliant with CNSA 2.0 and NIST standards, including ML-KEM and ML-DSA algorithms. It emphasizes crypto-agility, secure boot, hardware root of trust, and hybrid security models—making it ideal for datacenter, industrial, and communications infrastructure applications.
MPESTI Interoperability with Nuvoton and Renesas Fanout Controller Demo
This demo showcases Lattice Semiconductor’s implementation of the Modular Peripheral Sideband Tunneling Interface (MPESTI), a single-wire communication protocol developed under the Open Compute Project (OCP). It highlights seamless interoperability between a MPESTI Initiator and multiple target devices from Nuvoton and Renesas, connected via a fanout controller on the Lattice iCE40 UltraPlus™ board. The setup supports up to 64 endpoints, enables hot-plug capability, and eliminates the need for external MUX or switches—offering a scalable, cost-efficient solution for modular data center environments.
Onboarding LTPI Demo
The Onboarding LTPI Demo showcases Lattice’s seamless Plug and Play setup for Host Processor Module (HPM) endpoints using JSON-based onboarding. It highlights how LTPI bridges hardware differences between HPM and DC-SCM modules by combining I2C, UART, and GPIO into a unified high-speed interface. The demo features dynamic metadata capture, pre-link endpoint detection via a RISC-V I2C controller, and sensor interaction through a Raspberry Pi acting as a BMC—demonstrating scalable, interoperable integration for modern data center ecosystems.
Quantum Secure Key Exchange Demo
This demo showcases the establishment of a quantum-resistant secure communication channel using post-quantum cryptography (PQC) on the Lattice MachXO5™-55TDQ FPGA. It features ML-KEM for key exchange and ML-DSA for digital signing, simulating secure boot, mutual authentication, and encrypted data exchange over I2C. The setup includes pre-provisioned public keys, protection against impersonation and replay attacks, and aligns with SPDM 1.4 standards. Designed for crypto agility, the demo highlights Lattice’s commitment to future-proof firmware security in datacenter, industrial, and communications applications.
SEC-TPM with Lattice MachXO5™-NX
The SEC-TPM Demo showcases a single-chip Root of Trust solution, integrating traditional TPM functionality with post-quantum cryptography (PQC) and Platform Firmware Resilience (PFR). Running on a RISC-V core, the demo highlights secure credential management anchored to hardware, leveraging Lattice’s RNG and crypto-agile architecture. It eliminates the need for external TPM chips, simplifying the supply chain and enabling secure remote updates—making it ideal for next-generation server security applications.
Single Chip Solution for Attestation Verifier, PFR, and LTPI Demo
This demo showcases Lattice’s unified security solution built on the Lattice MachXO5™-NX 55TDQ device, integrating attestation verifier, Platform Firmware Resilience (PFR), and LTPI capabilities into a single chip. Leveraging the Lattice Sentry™ 4.0 platform, it supports both traditional cryptography and post-quantum algorithms (ML-DSA, ML-KEM), enabling secure image authentication, key exchange, and encrypted communication. The solution is compliant with SPDM 1.2, NIST 800-193, and CNSA 2.0 standards, and offers robust connectivity via I2C, I3C, SMBus, and LTPI—delivering scalable, crypto-agile protection for modern server platforms.
SPDM 1.2 Demo
The SPDM 1.2 Demo showcases the Lattice Sentry™ 4.0 platform’s robust hardware and firmware security capabilities through cryptographic attestation. Running on the Lattice MachXO5™-NX 55TDQ device, the demo verifies device identity and firmware integrity using SPDM 1.2 commands over I2C and I3C interfaces, including LTPI channels. It highlights a modular framework designed for future security upgrades, including SPDM 1.4 and post-quantum cryptography (PQC) with ML-KEM and ML-DSA support—demonstrating Lattice’s commitment to evolving cybersecurity standards.
USB to I/O Conversion Demo
The USB to I/O Conversion Demo showcases Lattice’s high-speed USB 2.0 connectivity solution built on the Lattice CrossLinkU™-NX FPGA, enabling seamless bridging between modern computing platforms and essential peripherals like GPIO, UART, and I2C. Supporting both CDC and MCTP USB classes, the demo highlights a scalable multi-endpoint architecture that manages up to three USB devices, ensuring robust system management and protocol flexibility. Designed for multi-node environments, this modular solution empowers developers with crypto-agile control and future-ready integration across industrial, embedded, and server applications.
Industrial HMI Demo: Intelligent Operator Recognition and Control
Experience a cutting-edge industrial human-machine interface (HMI) that features advanced operator attention sensing and identification. This demo enables seamless interaction with machinery, delivering real-time insights and precise control for enhanced operational efficiency.
Lattice Semiconductor: Advancing Low Power FPGA Leadership
As the low power programmable leader, Lattice is at the forefront of FPGA innovation. We're committed to delivering industry-leading low power, high-performance, small footprint solutions as a steadfast, trustworthy partner to our customers worldwide.
Lattice Nexus™ 2 FPGA Platform
What’s New in Lattice Radiant™ 2024.2
Lattice Nexus™ 2 FPGA Platform: Power and Performance Leadership Demonstration
Lattice Nexus™ 2 FPGA Platform: Boot Up Demonstration
Lattice Nexus™ 2 FPGA Platform: Edge Sensor Monitoring Demonstration
Lattice Avant™-X FPGA: SERDES Demo
Lattice Avant™-X FPGA: Power Efficiency Demo
Lattice Avant™-G FPGA: Boot Up Time Demo
Glance by Mirametrix® Demonstration: Enhancing Safety and Reducing Errors in Industrial Applications
2023 Lattice Developers Conference: Opening Keynotes
Innovative Mid-Range FPGAs: Lattice Avant™-G and Lattice Avant™-X
Lattice Drive™ Solution Stack - Accelerate Automotive Application Development
Lattice Radiant – FPGA Design Complete Tools Suite
Lattice Semiconductor: Expanding Our FPGA Leadership
Accton Technology: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
NI: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
Rockwell Automation: Power Efficient FPGA Solutions, Lattice Avant™
Lattice Ecosystem Partners Share Excitement on Lattice Avant™
Lattice Avant™ FPGA Platform: AI Processing Demo
Lattice Avant™ FPGA Platform: Performance Demo
Lattice Avant™ FPGA Platform: Power Efficiency Demo
Lattice Avant™: The Next Level of FPGA Innovation
Lattice Avant™ FPGA Platform: Taking Low Power to New Heights
Lattice Semiconductor: Keynote Address at Embedded World 2022
Interview with Lattice Semiconductor: How FPGAs Solve Today’s Technology Trend Challenges
ラティス・ネクサス・プラットフォームの紹介
CrossLink-NXの紹介
CrossLink-NX: エネルギー効率・デモ
CrossLink-NX: インスタントオン・デモ
ラティスセミコンダクター: 低消費電力プログラマブルソリューションのリーディングカンパニー
ラティス MachXO3D: セキュアシステム開発を実現
ラティスsensAI: エッジアプリケーション向け低消費電力AIを実現
eARCが簡単に実現するまるで映画館にいるようなサラウンドシステム
- 広帯域幅 - すべてのオーディオフォーマットに対応する37Mのオーディオ
- テレビを簡単に操作できる完全なホームシアター体験
- ビデオ規格の変更にも対応し、将来的に使い続けられるレシーバ
ECP5を使った繋ぎ目のない360度サラウンドビューの実現
Face Tracking Using ECP5 and CNNs | Lattice sensAI
This demonstration identifies and tracks a human face. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
ECP5 と CNN を使った人感検出 | ラティスsensAI
ECP5とCNNを使ったオブジェクトカウント | ラティスsensAI
ECP5とCNNを使った速度標識検出 | ラティスsensAI
このデモンストレーションでは、制限速度標識と標識に記載されていることを認識します。ECP5が搭載されたエンベデッドビジョン開発キットに実装された8つの畳み込みニューラルネットワークを使って推論を行います。消費電力は1W以下です。
エンベデッドビジョンアプリケーション向け評価ソリューション
モジュール型 VIP プラットフォームを使用して、複数の入出力I/Oを簡単に組み合わせることができます。
- 入力オプション: HDMI、ディスプレイポート、デュアルセンサー
- 出力オプション: HDMI、ディスプレイポート、USB3-GbE
MIPI DSI - LVDS 変換をCrossLinkで実現
オールウェイズ・オン処理のデモ
ラティス CrossLink FPGA を使った 360° サラウンドビューアプリケーション
ラティス Radiant 開発ソフトウェアで精度の高いデザインを実現
Lattice Autonomous Robot Demo
HDMI 2.1 eARCによってオーディオ接続を簡素化
モバイル対応機器向けCrossLink IPコア
ラティスエンベデッドビジョン開発キット
CrossLink FPGAの低電力、小型フォームファクタECP5のブリッジ機能と、HDMI ASSPの高解像度の利点をこのモジュラープラットフォームに組み合わせました。この開発キットの仕様を参照して、ロボット、ドローン、ADAS、スマート・サーベイランス、AR / VRシステムの柔軟な接続とエネルギー効率の良い画像処理を可能にする方法をご覧ください。
Embedded World 2017にラティスが参加
接続性と処理に最適なエッジ製品ソリューションを展示しました
CrossLink 4：1 CSI-2 アグリゲータ IPデモ
ドローン、AR / VR、360カメラ、その他の自動車および産業用ソリューションに最適なラティスのCrossLink FPGAと、新しい4：1 MIPI CSI-2カメラアグリゲータブリッジについて学んでください。
エンベデッドビジョンソリューション
ラティスの製品がエッジコンピューティングアプリケーション（ビデオ処理アクセラレーション）、マシンビジョンのセンサーブリッジ、ロボットとドローンのステレオビジョンに対応する方法を紹介します
自動車FPGA
最新の先進運転支援システム（ADAS）のニーズをFPGAがどのように対応するかご覧になれます
ラティスの製品を用いたロボットのステレオビジョン
ラティスCrossLink FPGA、ECP5 FPGA、HDMI ASSPは、ビデオ処理と配信向けの完全で効率的なソリューションを提供します
ADAS向け車載機器ソリューション
ECP5 FPGAデバイスを使用して、複数の車載機器用のカメラの画像を取り込み、それらをつなぎ合わせて、多くの強化/補正機能を利用して、最終的にドライバーの1つの鮮やかな画像を出力することができます
iCE40 FPGAによる信号集約ソリューション
iCE40 UltraPlusは、システムコストと消費電力を低減し、市場投入までの時間を短縮するため、メモリとDSPを強化した世界最小のFPGAです。エンベデッドRISC-Vとマルチセンサアグリゲーションデモのセンサデータフュージョンが、なぜiCE40 UltraPlusは次のコンシューマ機器にとって必要不可欠なのか紹介します
ラティスのソリューションを使った信号集約
ラティスのiCE40 FPGAを製品に使ったビデオおよびオーディオ信号集約を紹介
ラティス iCE40 FPGAによる信号集約ソリューション
iCE40 UltraPlusは、システムコストを消費電力を低減し、市場投入までの時間を短縮するために、メモリとDSPを強化した世界最小のFPGAです。エンベデッドRISC-Vとマルチセンサアグリゲーションにおけるセンサデータフュージョンのデモが、なぜiCE40 UltraPlusは次のコンシューマ機器にとって必要不可欠なのか紹介します
iCE40 UltraPlusの利点デモ
LPモードとHSモードのMIPI D-PHYに対応した最初のiCE40製品であるiCE40 UltraPlusをご覧ください。このビデオでは、MIPI DSIディスプレイとフレームバッファリング用の統合SRAMメモリの駆動など、追加の利点について説明します
カメラ用マルチCSI-2ブリッジ
カメラのインターフェイスがアプリケーションプロセッサのインターフェイスと一致しない場合はブリッジが必要です。一般的なアプリケーション例は、複数のMIPI CSI-2イメージセンサを多重化または組み合わせ、それらを1つのMIPI CSI-2出力に結合することです。CrossLinkソリューションは、ドローン、360度カメラ、アクションカメラ、監視カメラ、拡張現実（AR）アプリケーションに使用されるカメラアグリゲーターです
ECP5 - FPGA ファミリ
ECP5 FPGAファミリは、すべてのFPGAが最も高い密度、消費電力、および高価でなければならないというルールを打ち破っています。小型で大容量のアプリケーションに焦点を当て、ラティスはECP5アーキテクチャを低コスト、小型フォームファクタ、低消費電力で最適化しました。これらの特性により、ECP5デバイスは、ASICおよびASSPに準拠するプログラマブルな接続ソリューションを提供するのに最適です
MachXO2 - 概要
MachXO2製品ファミリの概要を参照しましょう。MachXO2がコストと電力を削減し、システム機能の統合を小型パッケージで実現した方法をご覧ください。MachXO2デバイスの設計を、無料のデザインツール、IPトライアル、リファレンスデザインで簡単に開始する方法を紹介します。
Clarity Designer を使った CrossLink IP の追加方法
What’s New in Lattice Radiant 2025.2
Lattice Radiant 2025.2 focuses on improvement in debugging, ease of use and designer productivity. Download Radiant now to explore more features.
What’s New in Lattice Propel 2025.2
Lattice Propel 2025.2 focuses on improved design creation and accelerated project startup. Download Propel now to explore more features.
