# PCI Express X4 IP Core

Implementing the IP Module Using ispLEVER

Instantiating the Core

The generated PCI Express X4 IP core package includes black-box (<user_name>_bb.v) and instance (<username>_inst.v) templates that can be used to instantiate the core in a top-level design. An example RTL top-level reference source file that can be used as an instantiation template for the IP core is provided in \<project_dir>\pcie_x4_eval\<username>\src\top. Users may also use this top-level reference as the starting template for the top-level for their complete design.

Implementing the Core in a Top-Level Design

As described previously, the top-level file <username>_top.v provided in \<project_dir>\pcie_x4_eval\<username>\src\top supports the ability to implement just the PCI Express X4 Block. Push-button top-level implementation of this top-level is supported via the ispLEVER project file pcie_x4_eval.syn located in \<project_dir>\pcie_x4_eval\<username>\impl. This design is intended only to provide an accurate indication of the device utilization associated with the core itself and should not be used as an actual implementation example.
To use the project file: Select Open Project under the File tab in ispLEVER. Browse to \<project_dir>\pcie_x4_eval\<username>\impl in the Open Project dialog box. Select and open pcie_x4_eval.syn. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project. An lpf files is available in the \impl directory pcie_x4_eval.lpf. Implement the complete design via the standard ispLEVER GUI flow. All other options remain at their default values.

Running Functional Simulation

The functional simulation includes a configuration-specific behavioral model of the PCI Express X4, which is instantiated in an FPGA top level along with some test logic (PLLs, UMI and Sysbus). This FPGA top is instantiated in an eval testbench that configures FPGA test logic registers and PCI Express X4 IP core registers. The testbench files can be found in \<project_dir>\pcie_x4_eval\testbench.
The generated IP core package includes the configuration-specific behavior model (<username>_beh.v) for functional simulation in \<project_dir>\pcie_x4_eval\src\beh_rtl\<family>. ModelSim simulation is supported via testbench files provided in \<project_dir>\pcie_x4_eval\<username>\testbench. Models required for simulation are provided in the corresponding \models folder. Users may run the eval simulation by doing the following: Open ModelSim. Under the File tab, select Change Directory Set the directory to \<project_dir>\pcie_x4_eval\<username>\sim\modelsim\rtl. Select OK. Under the Tools tab, select TCL, then select Execute Macro. Go back to modelsim dir(one level up). Double-click the "script" folder. Select file eval_beh_rtl.do NOTE1: When the simulation completes, a pop-up window will appear asking "are you sure you want to finish?" Answer "no" to analyze the results (answering "yes" closes ModelSim). NOTE2: Simulation will only be available for the default configuration.

Running Timing Simulation

Users may run the eval timing simulation by doing the following: In ispLever, after the "Place & Route Design" is done, double click the "Generate Timing simulation Files" to get the VO & SDF file for timing simulation. Open ModelSim. Under the File tab, select Change Directory Set the directory to \<project_dir>\pcie_x4_eval\<username>\sim\modelsim\timing. Select OK. Under the Tools tab, select TCL, then select Execute Macro. Go back to modelsim dir(one level up). Double-click the "script" folder. Select file eval_gate.do NOTE1: When the simulation completes, a pop-up window will appear asking "are you sure you want to finish?" Answer "no" to analyze the results (answering "yes" closes ModelSim). NOTE2: Simulation will only be available for the default configuration.

Timing Report file

IP cores are usually over constrained to achieve better timing performance. Hence, the user may observe timing violations when viewing the timing report.

For some cores, separate Post Route Trace preference files are provided to generate the correct timing report.

1) Replace the preference file (.prf) in the project directory with the following Post Route Trace file. Rename the Post Route Trace preference file to match the project name.

- <username>_eval_final.prf

2) From the GUI of the Project Navigator, right click on Place_Route_Trace_Report. Select Force One Level

- The new timing report is generated.

Other Core-specific Notes

N/A

Reference Information
The following documents provide more information on implementing this core:

- User's Guide
- IPexpress Quick Start Guide

General Information

Copyright Notice

Copyright 2000-2007© Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.

Contacting Lattice

Mail: | Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 U.S.A.
Telephone: | 1-800-LATTICE (USA and Canada)
| 1-503-268-8001 (other locations)
Website: | http://www.latticesemi.com(US) http://www.latticesemi.com.cn(China) http://www.latticesemi.co.kr(Korea) http://www.latticesemi.co.jp(Japan)
E-mail: | techsupport@latticesemi.com techsupport_china@latticesemi.com (China)

IP Module Information

About this Module

IP Name: | PCI Express X4
IP Version: | ver 3.1
IP Release Date: | Jul 2007
Target Technology: | Lattice SCM

Software Requirements

Synthesis Tools Supported: | Synplify 8.8L2 Precision 2006a2.19OEM_Lattice
Simulation Tools Supported: | Modelsim 6.2g
Lattice Tool Supported: | ispLever7.0 or later