#-- Synplicity, Inc.
#-- Version Synplify for Lattice 8.8L2
#-- Project file U:\jafa\devices\slayer\S041YO~C\D7B28O~S.1\PFVIK4~D\SXRGDC~0\run_options.txt
#-- Written on Mon Nov 12 09:53:46 2007


#add_file options
add_file -verilog "C:/ispTOOLS7_0_CD/ispcpld/../cae_library/synthesis/verilog/scm.v"
add_file -verilog "top.h"
add_file -verilog "../src/uml/uml.v"
add_file -verilog "../src/gen/sysbus.v"
add_file -verilog "../src/wbs_16kebr/gen/dpram4kx32.v"
add_file -verilog "../src/wbs_16kebr/wbs_16kebr.v"
add_file -verilog "../src/wbs_gpio/wbs_gpio.v"
add_file -verilog "../src/wb_dec/wb_dec.v"
add_file -verilog "../src/wb_intf/tx_tlp_ctrl.v"
add_file -verilog "../src/wb_intf/gen/fifo4kx36to72.v"
add_file -verilog "../src/wb_intf/mem_read_fifo.v"
add_file -verilog "../src/wb_intf/comp_gen.v"
add_file -verilog "../src/wb_intf/mem_wr.v"
add_file -verilog "../src/wb_intf/gen/fifo1kx7.v"
add_file -verilog "../src/wb_intf/gen/fifo4kx72to36.v"
add_file -verilog "../src/wb_intf/mem_req_fifo.v"
add_file -verilog "../src/wb_intf/rx_tlp_decode.v"
add_file -verilog "../src/wb_intf/wbm_tlpproc.v"
add_file -verilog "../src/ip_tx_arbiter.v"
add_file -verilog "../src/ur_gen/ur_gen.v"
add_file -verilog "../src/ip_rx_crpr.v"
add_file -verilog "../src/pcie_soft/pcie_bb.v"
add_file -verilog "../src/gen/pll_61.v"
add_file -verilog "../src/led_status.v"
add_file -verilog "../src/top.v"


#implementation: "SXRGDC~0"
impl -add SXRGDC~0 -type fpga

#device options
set_option -technology LATTICE-scm
set_option -part LFSCM3GA25EP1
set_option -package F256C
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "top"

#map options
set_option -frequency 200.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -force_gsr auto


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./top.edi"

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0
set_option -auto_constrain_io true
impl -active "SXRGDC~0"
