`timescale 1ns/10ps

module cjpat_genchk(

	//--- data/control output ---
	cjpat_chk_data_8b,
	cjpat_chk_ctl,

	//--- data/control output ---
	cjpat_gen_data_8b,
	cjpat_gen_ctl,

	//--- misc control ---
	tclk,
	rclk,
	sys_reset_z, 
	inj_err_n,

	error,
	errorcnt,
	clear_error_n
	
          );      


input  inj_err_n;


//--- data/control output ---
output	[7:0]	cjpat_gen_data_8b;
output		cjpat_gen_ctl;


//new stuff for programability

output   error;
output   [7:0] errorcnt;

input    clear_error_n;


//--- data/control output ---
input	[7:0]	cjpat_chk_data_8b;
input		cjpat_chk_ctl;

//--- misc control ---
input		tclk;
input		rclk;
input		sys_reset_z;	//system reset
//------------ end of I/O list --------------------------------------





//generator


cjpat_gen cjpat_gen_i(

	//--- data/control output ---
	cjpat_gen_data_8b,
	cjpat_gen_ctl,

	//--- misc control ---
	tclk,
	sys_reset_z, 
	inj_err_n
          );   
          


cjpat_chk cjpat_chk_i(

	//--- data/control output ---
	cjpat_chk_data_8b,
	cjpat_chk_ctl,

	//--- misc control ---
	rclk,
	sys_reset_z, 
	error,
	errorcnt,
	clear_error_n
          );      
   

endmodule
