module sc_orcastra(rstn,
                   umi_rdata, umi_wdata, umi_addr, umi_clk, umi_wr_n, umi_rdy, umi_retry, umi_err, umi_ack,
                   tck, tdi, tms, tdo
                   );

input rstn;
input  [7:0]  umi_rdata;
output [7:0]  umi_wdata;
output [17:0] umi_addr;
output umi_clk;
output umi_wr_n;
output umi_rdy;
input umi_ack, umi_retry, umi_err;
input tck, tdi, tms;
output tdo;


reg           PC_Ready ;
reg [31:0]    BSRing1 ;
reg [26:0]    DataInReg ;
reg [4:0]     c ;
wire          ClkEn ;
wire [7:0]    DataOut ;

reg   umi_wr_n ;
reg   UMackReg ;
reg   UMretryReg ;
reg   UMerrReg ;
reg   UMready2 ;

reg   PCready2 ;
reg   PCready3 ;
reg   PCready4 ;
wire   UMset ;
wire   UMclear ;
reg   umi_rdy ;
reg   UMlockI ;


JTAGA jtag(

  .TCK(tck),
  .TDI(tdi),
  .TDO(tdo),
  .TMS(tms),

  .PSROUT1(PSR_Out1),
  .PSROUT2(1'b0),
  .PSROUT3(1'b0),
//  .JTDO1(JTDO),
  .JTDO1(1'b0),
  .JTDO2(1'b0),
  .JTDO3(1'b0),
  .JTDO4(1'b0),
  .JTDO5(1'b0),
  .JTDO6(1'b0),
  .JTDO7(1'b0),
  .JTDO8(1'b0),
  .TRESET( ),
  .PSRSFTN(Shift_DR),
  .PSRCAP(Capture_DR),
  .PSRENABLE1(PSR_Enable1),
  .PSRENABLE2( ),
  .PSRENABLE3( ),
  .SCANENABLE1( ),
  .SCANENABLE2( ),
  .SCANENABLE3( ),
  .SCANENABLE4( ),
  .SCANENABLE5( ),
  .SCANENABLE6( ),
  .SCANENABLE7( ),
  .SCANENABLE8( ),
  .SCANI(),
  .JTCK(JTCK),
  .JTDI(JTDI),
  .JSHIFT( ),
  .JUPDATE( ),
  .JRSTN( ),
  .JCE1( ),
  .JCE2( ),
  .JCE3( ),
  .JCE4( ),
  .JCE5( ),
  .JCE6( ),
  .JCE7( ),
  .JCE8( ),
  .JRTI1( ),
  .JRTI2( ),
  .JRTI3( ),
  .JRTI4( ),
  .JRTI5( ),
  .JRTI6( ),
  .JRTI7( ),
  .JRTI8( )
); 
    
always @(posedge JTCK or posedge Capture_DR)
begin
    if (Capture_DR)
    begin
      c <= 5'b00000;
    end
    else if (~Shift_DR & PSR_Enable1)
    begin
      c <= c + 1;
    end
end
    
always @(posedge JTCK or negedge rstn)
begin
    if (~rstn)
    begin
       PC_Ready <= 1'b0 ;
       DataInReg <= 27'h0000000 ;
       BSRing1 <= 32'h00000000 ;
    end
    else if (PSR_Enable1 && ~Shift_DR)
    begin  
      if (c == 5'b11110)  
      begin
          PC_Ready <= 1'b0 ;
          DataInReg <= BSRing1[29:3] ;
      end
      else if (c == 5'b11111)
      begin
          PC_Ready <= BSRing1[30] ;
          BSRing1 <= ({19'b0000000000000000000, UMackReg, UMackReg, UMretryReg, UMerrReg, umi_rdata, 1'b0}) ;
      end
      else 
          BSRing1 <= ({JTDI, BSRing1[31:1]}) ; 
    end
end

assign PSR_Out1 = BSRing1[0] ;
assign umi_wdata = ({4'b0000, DataInReg[7:0],  DataInReg[7:0],  DataInReg[7:0],  DataInReg[7:0]})  ;
assign umi_addr = DataInReg[25:8] ;
assign PC_Read = DataInReg[26] ;

assign UMset = PCready3 & ~PCready4 ;
assign UMclear = ~PCready3 & PCready4 ;

OSCA osc(.OSC(umi_clk)); 

always @ (posedge umi_clk or negedge rstn)
begin
  if (~rstn)
    begin
       PCready2 <= 1'b0 ;
       PCready3 <= 1'b0 ;
       PCready4 <= 1'b0 ;
       umi_rdy <= 1'b0 ;
    end
  else
   begin
     PCready2 <= PC_Ready ;
     PCready3 <= PCready2 ;
     PCready4 <= PCready3 ;
     umi_rdy <= UMlockI & umi_ack & ~UMready2 ;
   end
end


always @ (posedge umi_clk or negedge rstn)
begin
   if (~rstn)
      UMready2 <= 1'b0 ;
   else if (UMclear)
      UMready2 <= 1'b0 ;
   else if (UMlockI && umi_ack)
      UMready2 <= 1'b1 ;
   else if (umi_ack && ~umi_rdy && UMready2)
       UMready2 <= 1'b0 ;
end

always @ (posedge umi_clk or negedge rstn)
begin
    if (~rstn)
       begin
         umi_wr_n <= 1'b0 ;
         UMlockI <= 1'b0 ;
       end 
    else if (UMclear)
       begin
         umi_wr_n <= 1'b0 ;
         UMlockI <= 1'b0 ;
       end
    else if (UMset)
       begin
         umi_wr_n <= ~PC_Read ;
         UMlockI <= 1'b1 ;
       end
    else if (umi_ack && ~umi_rdy && UMready2)
       begin
         umi_wr_n <= 1'b0 ;
         UMlockI <= 1'b0 ;
       end
end

always @ (posedge umi_clk or negedge rstn)
begin
   if (~rstn)
      begin
         UMackReg <= 1'b0 ;
         UMretryReg <= 1'b0 ;
         UMerrReg <= 1'b0 ;
      end 
   else if (UMclear)
      begin
         UMackReg <= 1'b0 ;
         UMretryReg <= 1'b0 ;
         UMerrReg <= 1'b0 ;
      end
   else if (umi_ack && ~umi_rdy && UMready2)
      begin
         UMackReg <= 1'b1 ;
         UMretryReg <= umi_retry ;
         UMerrReg <= umi_err ;
      end
end








endmodule