#define  _circuit_name  systembus
#define  _enable_mpi  1
#define  _bus_width   8
#define  _parity_enable  1
#define  _dma_interface  0
#define  _mpi_clk_async  0
#define  _enable_umi  1
#define  _enable_orcastra  0
#define  _umi_sync_hclk  0
#define  _auto_retry   1

#define  _enable_usi   1
#define  _usi_sync_hclk  0

#define  _enable_smi   0

#define  _enable_smi_port_0x410   0

#define  _enable_smi_port_0x420   0

#define  _enable_smi_port_0x430   0

#define  _enable_smi_port_0x440   0

#define  _enable_smi_port_0x450   0

#define  _enable_smi_port_0x460   0

#define  _enable_smi_port_0x470   0

#define  _enable_smi_port_0x480   0

#define  _enable_smi_port_0x490   0

#define  _enable_smi_port_0x4a0   0

#define  _enable_smi_port_0x4b0   0

#define  _enable_smi_port_0x4c0   0

#define  _enable_smi_port_0x4d0   0

#define  _enable_smi_port_0x4e0   0

#define  _enable_smi_port_0x4f0   0

#define  _enable_smi_port_0x500   0

#define  _enable_smi_port_0x510   0

#define  _enable_smi_port_0x520   0

#define  _enable_smi_port_0x530   0

#define  _enable_smi_port_0x540   0

#define  _enable_smi_port_0x550   0

#define  _enable_smi_port_0x560   0

#define  _enable_smi_port_0x570   0

#define  _enable_smi_port_0x580   0

#define  _enable_smi_port_0x590   0

#define  _enable_smi_port_0x5a0   0

#define  _enable_smi_port_0x5b0   0

#define  _enable_smi_port_0x5c0   0

#define  _enable_smi_port_0x5d0   0

#define  _enable_smi_port_0x5e0   0

#define  _enable_smi_port_0x5f0   0

#define  _enable_smi_port_0x600   0

#define  _enable_smi_port_0x610   0

#define  _enable_smi_port_0x620   0

#define  _enable_smi_port_0x630   0

#define  _enable_smi_port_0x640   0

#define  _enable_smi_port_0x650   0

#define  _enable_smi_port_0x660   0

#define  _enable_smi_port_0x670   0

#define  _enable_smi_port_0x680   0

#define  _enable_smi_port_0x690   0

#define  _enable_smi_port_0x6a0   0

#define  _enable_smi_port_0x6b0   0

#define  _enable_smi_port_0x6c0   0

#define  _enable_smi_port_0x6d0   0

#define  _enable_smi_port_0x6e0   0

#define  _enable_smi_port_0x6f0   0

#define  _enable_smi_port_0x700   0

#define  _enable_smi_port_0x710   0

#define  _enable_smi_port_0x720   0

#define  _enable_smi_port_0x730   0

#define  _enable_smi_port_0x740   0

#define  _enable_smi_port_0x750   0

#define  _enable_smi_port_0x760   0

#define  _enable_smi_port_0x770   0

#define  _enable_smi_port_0x780   0

#define  _enable_smi_port_0x790   0

#define  _enable_smi_port_0x7a0   0

#define  _enable_smi_port_0x7b0   0

#define  _enable_smi_port_0x7c0   0

#define  _enable_smi_port_0x7d0   0

#define  _enable_smi_port_0x7e0   0

#define  _enable_smi_port_0x7f0   0

#define _pcs_360	on

#define _pcs_361	off

#define _pcs_362	off

#define _pcs_363	off

#define _pcs_3e3	off

#define _pcs_3e2	off

#define _pcs_3e1	off

#define _pcs_3e0	on

#define _driver_group0 none

#define _driver_group1 none

#define _driver_group2 none

#define _driver_group3 none

#define  _enable_multi_align   0

#define  _read_parity   "EVEN"
#define  _mpi_priority  "LOW"
#define  _umi_priority   "LOW"
#define  _mpi_sys_reset   0
#define  _umi_sys_reset   0
#define  _sys_clock   "USER"
#define  _interrupt_vec1  00000000000000000000000000000000
#define  _interrupt_vec2  00000000000000000000000000000000
#define  _interrupt_vec3  00000000000000000000000000000000
#define  _interrupt_vec4  00000000000000000000000000000000
#define  _interrupt_vec5  00000000000000000000000000000000
#define  _interrupt_vec6  00000000000000000000000000000000
#define _syn_attr_option "synplicity"

#define _lang verilog

#include <sysbus/SYSBUS.v>
