
// This interface file generated using PCS Module-Gen: _kit_version

`timescale 1ns / 10 ps




module SC_top (
// serdes clk pins //
  refclk360p, refclk360n,
// Data to FPGA and SERDES //
  hdin360p_0, hdin360n_0, hdout360p_0, hdout360n_0,
  hdin360p_1, hdin360n_1, hdout360p_1, hdout360n_1,
  hdin360p_2, hdin360n_2, hdout360p_2, hdout360n_2,
  hdin360p_3, hdin360n_3, hdout360p_3, hdout360n_3,

// serdes clk pins //
  refclk3e0p, refclk3e0n,
// Data to FPGA and SERDES //
  hdin3e0p_0, hdin3e0n_0, hdout3e0p_0, hdout3e0n_0,
  hdin3e0p_1, hdin3e0n_1, hdout3e0p_1, hdout3e0n_1,
  hdin3e0p_2, hdin3e0n_2, hdout3e0p_2, hdout3e0n_2,
  hdin3e0p_3, hdin3e0n_3, hdout3e0p_3, hdout3e0n_3,
  
//system bus
  mpi_cs0n, mpi_cs1, mpi_clk, mpi_wr_n, mpi_strb_n, mpi_tsiz, mpi_burst, mpi_bdip,
  mpi_addr, mpi_data, mpi_par, mpi_rst_n, mpi_ta, mpi_retry, mpi_tea, mpi_irq_n,
 
//general IO
reset_n,

//PRBS IOS
Error360_0,
Error360_1,
Error360_2,
Error360_3,
Error3e0_0,
Error3e0_1,
Error3e0_2,
Error3e0_3,

//OUTPUT CLOCKS
//ref_pclk3e0,
//ref_pclk360, 
//rxa_pclk360,
//rxa_pclk3e0,

//JTAG
                   tck, tdi, tms, tdo


  );


//JTAG
input tck, tdi, tms;
output tdo;

//general io
input reset_n   ;

//PRBS IO  
output Error360_0;
output Error360_1;
output Error360_2;
output Error360_3;
output Error3e0_0;
output Error3e0_1;
output Error3e0_2;
output Error3e0_3; 

//OUTPUT CLOCKS
//output ref_pclk3e0;
//output ref_pclk360; 
//output rxa_pclk360;
//output rxa_pclk3e0;

  
  
input         refclk360n; // exemplar attribute refclkn NOPAD true
input         refclk360p; // exemplar attribute refclkp NOPAD true

input         hdin360p_0; // exemplar attribute hdinp_0 NOPAD true
input         hdin360n_0; // exemplar attribute hdinn_0 NOPAD true
output        hdout360p_0; // exemplar attribute hdoutp_0 NOPAD true
output        hdout360n_0; // exemplar attribute hdoutn_0 NOPAD true

input         hdin360p_1; // exemplar attribute hdinp_1 NOPAD true
input         hdin360n_1; // exemplar attribute hdinn_1 NOPAD true
output        hdout360p_1; // exemplar attribute hdoutp_1 NOPAD true
output        hdout360n_1; // exemplar attribute hdoutn_1 NOPAD true

input         hdin360p_2; // exemplar attribute hdinp_2 NOPAD true
input         hdin360n_2; // exemplar attribute hdinn_2 NOPAD true
output        hdout360p_2; // exemplar attribute hdoutp_2 NOPAD true
output        hdout360n_2; // exemplar attribute hdoutn_2 NOPAD true

input         hdin360p_3; // exemplar attribute hdinp_3 NOPAD true
input         hdin360n_3; // exemplar attribute hdinn_3 NOPAD true
output        hdout360p_3; // exemplar attribute hdoutp_3 NOPAD true
output        hdout360n_3; // exemplar attribute hdoutn_3 NOPAD true

input         refclk3e0n; // exemplar attribute refclkn NOPAD true
input         refclk3e0p; // exemplar attribute refclkp NOPAD true

input         hdin3e0p_0; // exemplar attribute hdinp_0 NOPAD true
input         hdin3e0n_0; // exemplar attribute hdinn_0 NOPAD true
output        hdout3e0p_0; // exemplar attribute hdoutp_0 NOPAD true
output        hdout3e0n_0; // exemplar attribute hdoutn_0 NOPAD true

input         hdin3e0p_1; // exemplar attribute hdinp_1 NOPAD true
input         hdin3e0n_1; // exemplar attribute hdinn_1 NOPAD true
output        hdout3e0p_1; // exemplar attribute hdoutp_1 NOPAD true
output        hdout3e0n_1; // exemplar attribute hdoutn_1 NOPAD true

input         hdin3e0p_2; // exemplar attribute hdinp_2 NOPAD true
input         hdin3e0n_2; // exemplar attribute hdinn_2 NOPAD true
output        hdout3e0p_2; // exemplar attribute hdoutp_2 NOPAD true
output        hdout3e0n_2; // exemplar attribute hdoutn_2 NOPAD true

input         hdin3e0p_3; // exemplar attribute hdinp_3 NOPAD true
input         hdin3e0n_3; // exemplar attribute hdinn_3 NOPAD true
output        hdout3e0p_3; // exemplar attribute hdoutp_3 NOPAD true
output        hdout3e0n_3; // exemplar attribute hdoutn_3 NOPAD true


//system bus
  input mpi_cs0n, mpi_cs1, mpi_clk, mpi_wr_n, mpi_strb_n, mpi_burst, mpi_bdip, mpi_rst_n;
  input [0:1] mpi_tsiz;
  input [14:31] mpi_addr;

  output mpi_ta, mpi_retry, mpi_tea, mpi_irq_n;
  inout [0:7] mpi_data;
  inout [0:0] mpi_par; 
  

  

//PCS 360

wire  [9:0] txd360_0;
wire  [9:0] txd360_1;
wire  [9:0] txd360_2;
wire  [9:0] txd360_3;

wire [44:0]  sysbus360_in;
wire [16:0]  sysbus360_out;

wire [9:0] rxd360_0;
wire [9:0] rxd360_1;
wire [9:0] rxd360_2;
wire [9:0] rxd360_3;

wire         tclk360_0, rclk360_0;
wire         tclk360_1, rclk360_1;
wire         tclk360_2, rclk360_2;
wire         tclk360_3, rclk360_3;

wire        ref_pclk360;

wire        ref_0_sclk360;
wire        ref_1_sclk360;
wire        ref_2_sclk360;
wire        ref_3_sclk360;

wire        rxa_pclk360;
wire        rxb_pclk360;

wire        rx_0_sclk360;
wire        rx_1_sclk360;
wire        rx_2_sclk360;
wire        rx_3_sclk360;


//PCS 3e0

wire  [9:0] txd3e0_0;
wire  [9:0] txd3e0_1;
wire  [9:0] txd3e0_2;
wire  [9:0] txd3e0_3;

wire [44:0]  sysbus3e0_in;
wire [16:0]  sysbus3e0_out;

wire [9:0] rxd3e0_0;
wire [9:0] rxd3e0_1;
wire [9:0] rxd3e0_2;
wire [9:0] rxd3e0_3;

wire         tclk3e0_0, rclk3e0_0;
wire         tclk3e0_1, rclk3e0_1;
wire         tclk3e0_2, rclk3e0_2;
wire         tclk3e0_3, rclk3e0_3;

wire        ref_pclk3e0;

wire        ref_0_sclk3e0;
wire        ref_1_sclk3e0;
wire        ref_2_sclk3e0;
wire        ref_3_sclk3e0;

wire        rxa_pclk3e0;
wire        rxb_pclk3e0;

wire        rx_0_sclk3e0;
wire        rx_1_sclk3e0;
wire        rx_2_sclk3e0;
wire        rx_3_sclk3e0;


//GLOBAL NETS
wire VHI=1;
GSR GSR_INST       (.GSR(reset_n));

wire   quad_rst, serdes_rst;
assign quad_rst=0;
assign serdes_rst=~reset_n;
wire  tx_rst, rx_rst;
assign tx_rst=~reset_n;
assign rx_rst=~reset_n;


assign  tclk360_0=  ref_pclk360;
assign  rclk360_0=  rx_0_sclk360;
assign  tclk360_1=  ref_pclk360;
assign  rclk360_1=  rx_1_sclk360;
assign  tclk360_2=  ref_pclk360;
assign  rclk360_2=  rx_2_sclk360;
assign  tclk360_3=  ref_pclk360;
assign  rclk360_3=  rx_3_sclk360;

assign  tclk3e0_0=  ref_pclk3e0;
assign  rclk3e0_0=  rx_0_sclk3e0;
assign  tclk3e0_1=  ref_pclk3e0;
assign  rclk3e0_1=  rx_1_sclk3e0;
assign  tclk3e0_2=  ref_pclk3e0;
assign  rclk3e0_2=  rx_2_sclk3e0;
assign  tclk3e0_3=  ref_pclk3e0;
assign  rclk3e0_3=  rx_3_sclk3e0;



PCS0 PCS0_360 (
// serdes clk pins //
  .refclkp (refclk360p), .refclkn (refclk360n), 

// Interface to SYSBUSA //
  .sysbus_in (sysbus360_in), .sysbus_out (sysbus360_out),
  .quad_rst (quad_rst), .serdes_rst (serdes_rst),
// Data to FPGA and SERDES //
//LANE 0
  .hdinp_0 (hdin360p_0 ), .hdinn_0 (hdin360n_0 ), 
  .hdoutp_0 (hdout360p_0 ), .hdoutn_0 (hdout360n_0 ),
   .txd_0 (txd360_0 ),  .rxd_0 (rxd360_0 ), 
  .tclk_0 (tclk360_0 ), .rclk_0 (rclk360_0 ),
  .ref_0_sclk (ref_0_sclk360 ), .rx_0_sclk (rx_0_sclk360 ),
  .rx_lsd_0(rx_lsd360_0), 
//LANE 1
  .hdinp_1 (hdin360p_1 ), .hdinn_1 (hdin360n_1 ), 
  .hdoutp_1 (hdout360p_1 ), .hdoutn_1 (hdout360n_1 ),
   .txd_1 (txd360_1 ),  .rxd_1 (rxd360_1 ), 
  .tclk_1 (tclk360_1 ), .rclk_1 (rclk360_1 ),
  .ref_1_sclk (ref_1_sclk360 ), .rx_1_sclk (rx_1_sclk360 ), 
  .rx_lsd_1(rx_lsd360_1), 
//LANE 2
  .hdinp_2 (hdin360p_2 ), .hdinn_2 (hdin360n_2 ), 
  .hdoutp_2 (hdout360p_2 ), .hdoutn_2 (hdout360n_2 ),
   .txd_2 (txd360_2 ),  .rxd_2 (rxd360_2 ), 
  .tclk_2 (tclk360_2 ), .rclk_2 (rclk360_2 ),
  .ref_2_sclk (ref_2_sclk360 ), .rx_2_sclk (rx_2_sclk360 ), 
  .rx_lsd_2(rx_lsd360_2), 
//LANE 3
  .hdinp_3 (hdin360p_3 ), .hdinn_3 (hdin360n_3 ), 
  .hdoutp_3 (hdout360p_3 ), .hdoutn_3 (hdout360n_3 ),
   .txd_3 (txd360_3 ),  .rxd_3 (rxd360_3 ), 
  .tclk_3 (tclk360_3 ), .rclk_3 (rclk360_3 ),
  .ref_3_sclk (ref_3_sclk360 ), .rx_3_sclk (rx_3_sclk360 ), 
  .rx_lsd_3(rx_lsd360_3), 


  .tx_rst_0 (tx_rst ), .rx_rst_0 (rx_rst ),
  .tx_rst_1 (tx_rst ), .rx_rst_1 (rx_rst ),
  .tx_rst_2 (tx_rst ), .rx_rst_2 (rx_rst ),
  .tx_rst_3 (tx_rst ), .rx_rst_3 (rx_rst ),
// misc signals to-from fpga //
  .ref_pclk (ref_pclk360 ), .rxa_pclk (rxa_pclk360 ), .rxb_pclk (rxb_pclk360 )  );
  


PCS0 PCS0_3e0 (
// serdes clk pins //
  .refclkp (refclk3e0p), .refclkn (refclk3e0n), 

// Interface to SYSBUSA //
  .sysbus_in (sysbus3e0_in), .sysbus_out (sysbus3e0_out),
  .quad_rst (quad_rst), .serdes_rst (serdes_rst),
// Data to FPGA and SERDES //
//LANE 0
  .hdinp_0 (hdin3e0p_0 ), .hdinn_0 (hdin3e0n_0 ), 
  .hdoutp_0 (hdout3e0p_0 ), .hdoutn_0 (hdout3e0n_0 ),
   .txd_0 (txd3e0_0 ),  .rxd_0 (rxd3e0_0 ), 
  .tclk_0 (tclk3e0_0 ), .rclk_0 (rclk3e0_0 ),
  .ref_0_sclk (ref_0_sclk3e0 ), .rx_0_sclk (rx_0_sclk3e0 ),
  .rx_lsd_0(rx_lsd3e0_0), 
//LANE 1
  .hdinp_1 (hdin3e0p_1 ), .hdinn_1 (hdin3e0n_1 ), 
  .hdoutp_1 (hdout3e0p_1 ), .hdoutn_1 (hdout3e0n_1 ),
   .txd_1 (txd3e0_1 ),  .rxd_1 (rxd3e0_1 ), 
  .tclk_1 (tclk3e0_1 ), .rclk_1 (rclk3e0_1 ),
  .ref_1_sclk (ref_1_sclk3e0 ), .rx_1_sclk (rx_1_sclk3e0 ), 
  .rx_lsd_1(rx_lsd3e0_1), 
//LANE 2
  .hdinp_2 (hdin3e0p_2 ), .hdinn_2 (hdin3e0n_2 ), 
  .hdoutp_2 (hdout3e0p_2 ), .hdoutn_2 (hdout3e0n_2 ),
   .txd_2 (txd3e0_2 ),  .rxd_2 (rxd3e0_2 ), 
  .tclk_2 (tclk3e0_2 ), .rclk_2 (rclk3e0_2 ),
  .ref_2_sclk (ref_2_sclk3e0 ), .rx_2_sclk (rx_2_sclk3e0 ), 
  .rx_lsd_2(rx_lsd3e0_2), 
//LANE 3
  .hdinp_3 (hdin3e0p_3 ), .hdinn_3 (hdin3e0n_3 ), 
  .hdoutp_3 (hdout3e0p_3 ), .hdoutn_3 (hdout3e0n_3 ),
   .txd_3 (txd3e0_3 ),  .rxd_3 (rxd3e0_3 ), 
  .tclk_3 (tclk3e0_3 ), .rclk_3 (rclk3e0_3 ),
  .ref_3_sclk (ref_3_sclk3e0 ), .rx_3_sclk (rx_3_sclk3e0 ), 
  .rx_lsd_3(rx_lsd3e0_3), 


  .tx_rst_0 (tx_rst ), .rx_rst_0 (rx_rst ),
  .tx_rst_1 (tx_rst ), .rx_rst_1 (rx_rst ),
  .tx_rst_2 (tx_rst ), .rx_rst_2 (rx_rst ),
  .tx_rst_3 (tx_rst ), .rx_rst_3 (rx_rst ),
// misc signals to-from fpga //
  .ref_pclk (ref_pclk3e0 ), .rxa_pclk (rxa_pclk3e0 ), .rxb_pclk (rxb_pclk3e0 )  );
  



//SB general signals;
wire sync_clk;
  wire  usr_irq_in, sysbus_rst_n;
  wire usr_irq_out;
 assign usr_irq_in=0;  
assign sysbus_rst_n=reset_n;  
 
  
//SB PCS  signals   
  wire [44:0] pcs360_out;
  wire [16:0] pcs360_in;

  wire [44:0] pcs3e0_out;
  wire [16:0] pcs3e0_in;


assign sysbus3e0_in= pcs3e0_out;
assign pcs3e0_in= sysbus3e0_out;


assign sysbus360_in= pcs360_out;
assign pcs360_in= sysbus360_out;


//*********************************************//         
//Signals connected to the User Slave Interface//
//*********************************************//
wire  	[35:0]	usi_rdata		; 
wire	        usi_clk			;		 
wire	        usi_rst_n		;  		 
wire	        usi_ack			;		
wire	        usi_retry = 1'b0	; 		 
wire	        usi_err = 1'b0	;  		 
wire	        usi_irq = 1'b0	;
wire	[35:0]  usi_wdata		; 
wire	[17:0]  usi_addr			; 
//wire	        usi_burst		;  		 
wire	        usi_rdy			;		 
wire	        usi_wr_n			; 		 
wire	[1:0]   usi_size			; 
//**********************************************//
//**********************************************//
assign usi_clk = sync_clk; 
assign usi_rst_n = reset_n; 

//**********************************************//         
//Signals connected to the User Master Interface//
//**********************************************//
wire [17:0]umi_addr   		;
wire [35:0]umi_wdata  		;
wire umi_clk          		;
wire umi_rst_n        		;
wire umi_wr_n         		;
wire umi_burst     =  1'b0	;
wire umi_rdy        		;
wire [1:0]umi_size = 2'b00   ;
wire umi_lock =1'b0         		;
wire umi_irq       = 1'b0    ;
wire [35:0]umi_rdata  		;
//wire umi_granted      		;
wire umi_ack          		;
wire umi_retry        		;
wire umi_err          		;
//***********************************************//
//***********************************************//
//assign umi_clk = sync_clk; 
assign umi_rst_n = reset_n; 

//**********************************************//         
//Signals specific to the Orcastra Interface//
//**********************************************//
wire [7:0]orc_wdata  		;
wire [7:0]orc_rdata  		;

assign umi_wdata[35:32]= 0;
assign umi_wdata[31:0]= {orc_wdata,orc_wdata,orc_wdata,orc_wdata};

assign  orc_rdata = umi_rdata[7:0];




  

systembus systembus_i (
  .mpi_cs0n(mpi_cs0n), .mpi_cs1(mpi_cs1),.mpi_clk(mpi_clk),.mpi_wr_n(mpi_wr_n), 
  .mpi_strb_n(mpi_strb_n), .mpi_tsiz(mpi_tsiz), .mpi_burst(mpi_burst),
   .mpi_bdip(mpi_bdip), .mpi_addr(mpi_addr), .mpi_data(mpi_data), .mpi_par(mpi_par), 
  .mpi_rst_n(mpi_rst_n), .mpi_ta(mpi_ta), .mpi_retry(mpi_retry), .mpi_tea(mpi_tea), 
  .mpi_irq_n(mpi_irq_n), .usr_irq_in(usr_irq_in), .sysbus_rst_n(sysbus_rst_n), 
  .usr_irq_out(usr_irq_out),  .sync_clk(sync_clk), .pcs360_out(pcs360_out),
  .pcs360_in(pcs360_in),
.pcs3e0_out(pcs3e0_out),
  .pcs3e0_in(pcs3e0_in),  
//  .ff_refclk(ff_refclk), .ff_refclk_out_l(ff_refclk_out_l)
  //, .ff_refclk_out_r(ff_refclk_out_r)
  
    .umi_addr(umi_addr), 
    .umi_wdata(umi_wdata), 
    .umi_size(umi_size), 
    .umi_clk(umi_clk), 
    .umi_rst_n(umi_rst_n), 
    .umi_wr_n(umi_wr_n), 
    .umi_burst(umi_burst), 
    .umi_rdy(umi_rdy), 
    .umi_lock(umi_lock), 
    .umi_irq(umi_irq),
    .umi_rdata(umi_rdata), 
    .umi_ack(umi_ack), 
    .umi_retry(umi_retry), 
    .umi_err(umi_err), 
    .usi_rdata(usi_rdata), 
    .usi_clk(usi_clk), 
    .usi_rst_n(usi_rst_n), 
    .usi_ack(usi_ack), 
    .usi_retry(usi_retry), 
    .usi_err(usi_err), 
    .usi_irq(usi_irq),
    .usi_wdata(usi_wdata), 
    .usi_addr(usi_addr), 
    .usi_size(usi_size), 
    .usi_rdy(usi_rdy), 
    .usi_wr_n(usi_wr_n),
    .usr_clk(umi_clk)
  );


sc_orcastra sc_orcastra_i(
		  .rstn(umi_rst_n),
                   .umi_rdata(orc_rdata), 
                   .umi_wdata(orc_wdata),
                    .umi_addr(umi_addr), 
                    .umi_clk(umi_clk), 
                    .umi_wr_n(umi_wr_n),
                     .umi_rdy(umi_rdy),
                      .umi_retry(umi_retry),
                       .umi_err(umi_err),
                        .umi_ack(umi_ack),
                       
                   .tck(tck),
                    .tdi(tdi),
                     .tms(tms), 
                     .tdo(tdo)

                   );
                   
                   


wire sw_inj_err_360;
wire sw_enable_360;
wire sw_clear_err_360;
wire sw_select_prbs_31_360;

wire sw_inj_err_3e0;
wire sw_enable_3e0;
wire sw_clear_err_3e0;
wire sw_select_prbs_31_3e0;



//wire		Reset_n=reset_n;	//system reset



//--- data/control output ---
wire	[9:0]	D_Out360;
assign txd360_0 = {D_Out360[0],D_Out360[1],D_Out360[2],D_Out360[3],D_Out360[4],D_Out360[5],D_Out360[6],D_Out360[7],D_Out360[8],D_Out360[9]};
assign txd360_1 = {D_Out360[0],D_Out360[1],D_Out360[2],D_Out360[3],D_Out360[4],D_Out360[5],D_Out360[6],D_Out360[7],D_Out360[8],D_Out360[9]};
assign txd360_2 = {D_Out360[0],D_Out360[1],D_Out360[2],D_Out360[3],D_Out360[4],D_Out360[5],D_Out360[6],D_Out360[7],D_Out360[8],D_Out360[9]};
assign txd360_3 = {D_Out360[0],D_Out360[1],D_Out360[2],D_Out360[3],D_Out360[4],D_Out360[5],D_Out360[6],D_Out360[7],D_Out360[8],D_Out360[9]};



//--- data input ---
wire	[9:0]	D_In_360_0;
assign D_In_360_0 = {rxd360_0[0],rxd360_0[1],rxd360_0[2],rxd360_0[3],rxd360_0[4],rxd360_0[5],rxd360_0[6],rxd360_0[7],rxd360_0[8],rxd360_0[9]};
wire	[9:0]	D_In_360_1;
assign D_In_360_1 = {rxd360_1[0],rxd360_1[1],rxd360_1[2],rxd360_1[3],rxd360_1[4],rxd360_1[5],rxd360_1[6],rxd360_1[7],rxd360_1[8],rxd360_1[9]};
wire	[9:0]	D_In_360_2;
assign D_In_360_2 = {rxd360_2[0],rxd360_2[1],rxd360_2[2],rxd360_2[3],rxd360_2[4],rxd360_2[5],rxd360_2[6],rxd360_2[7],rxd360_2[8],rxd360_2[9]};
wire	[9:0]	D_In_360_3;
assign D_In_360_3 = {rxd360_3[0],rxd360_3[1],rxd360_3[2],rxd360_3[3],rxd360_3[4],rxd360_3[5],rxd360_3[6],rxd360_3[7],rxd360_3[8],rxd360_3[9]};


//--- misc control ---
wire		Tclk360=ref_pclk360;
//wire		Rclk360_0=rclk360_0;
//wire		Rclk360_1=rclk360_1;
//wire		Rclk360_2=rclk360_2;
//wire		Rclk360_3=rclk360_3;

wire	[7:0]	ErrorCnt360_0;
wire	[7:0]	ErrorCnt360_1;
wire	[7:0]	ErrorCnt360_2;
wire	[7:0]	ErrorCnt360_3;


prbs_quad prbs_quad_360(

    .Reset_n(reset_n) ,
    .Tclk(Tclk360) ,
    .Rclk_0(rclk360_0) ,
    .Rclk_1(rclk360_1) ,
    .Rclk_2(rclk360_2) ,
    .Rclk_3(rclk360_3) ,
    .Enable(sw_enable_360) ,
    .D_In_0(D_In_360_0) ,
    .D_In_1(D_In_360_1) ,
    .D_In_2(D_In_360_2) ,
    .D_In_3(D_In_360_3) ,
    .Err_Inj(sw_inj_err_360) ,
    .D_Out(D_Out360) ,
    .Error_0(Error360_0) ,
    .Error_1(Error360_1) ,
    .Error_2(Error360_2) ,
    .Error_3(Error360_3) ,
    .ErrorCnt_0(ErrorCnt360_0) ,
    .ErrorCnt_1(ErrorCnt360_1) ,
    .ErrorCnt_2(ErrorCnt360_2) ,
    .ErrorCnt_3(ErrorCnt360_3) ,
    .ClearErrorCnt(sw_clear_err_360) ,          
    .SelPRBS31(sw_select_prbs_31_360)   	
          );     



//--- data/control output ---
wire	[9:0]	D_Out3e0;
assign txd3e0_0 = {D_Out3e0[0],D_Out3e0[1],D_Out3e0[2],D_Out3e0[3],D_Out3e0[4],D_Out3e0[5],D_Out3e0[6],D_Out3e0[7],D_Out3e0[8],D_Out3e0[9]};
assign txd3e0_1 = {D_Out3e0[0],D_Out3e0[1],D_Out3e0[2],D_Out3e0[3],D_Out3e0[4],D_Out3e0[5],D_Out3e0[6],D_Out3e0[7],D_Out3e0[8],D_Out3e0[9]};
assign txd3e0_2 = {D_Out3e0[0],D_Out3e0[1],D_Out3e0[2],D_Out3e0[3],D_Out3e0[4],D_Out3e0[5],D_Out3e0[6],D_Out3e0[7],D_Out3e0[8],D_Out3e0[9]};
assign txd3e0_3 = {D_Out3e0[0],D_Out3e0[1],D_Out3e0[2],D_Out3e0[3],D_Out3e0[4],D_Out3e0[5],D_Out3e0[6],D_Out3e0[7],D_Out3e0[8],D_Out3e0[9]};



//--- data input ---
wire	[9:0]	D_In_3e0_0;
assign D_In_3e0_0 = {rxd3e0_0[0],rxd3e0_0[1],rxd3e0_0[2],rxd3e0_0[3],rxd3e0_0[4],rxd3e0_0[5],rxd3e0_0[6],rxd3e0_0[7],rxd3e0_0[8],rxd3e0_0[9]};
wire	[9:0]	D_In_3e0_1;
assign D_In_3e0_1 = {rxd3e0_1[0],rxd3e0_1[1],rxd3e0_1[2],rxd3e0_1[3],rxd3e0_1[4],rxd3e0_1[5],rxd3e0_1[6],rxd3e0_1[7],rxd3e0_1[8],rxd3e0_1[9]};
wire	[9:0]	D_In_3e0_2;
assign D_In_3e0_2 = {rxd3e0_2[0],rxd3e0_2[1],rxd3e0_2[2],rxd3e0_2[3],rxd3e0_2[4],rxd3e0_2[5],rxd3e0_2[6],rxd3e0_2[7],rxd3e0_2[8],rxd3e0_2[9]};
wire	[9:0]	D_In_3e0_3;
assign D_In_3e0_3 = {rxd3e0_3[0],rxd3e0_3[1],rxd3e0_3[2],rxd3e0_3[3],rxd3e0_3[4],rxd3e0_3[5],rxd3e0_3[6],rxd3e0_3[7],rxd3e0_3[8],rxd3e0_3[9]};



//--- misc control ---
wire		Tclk3e0=ref_pclk3e0;
//wire		Rclk3e0_0=rclk3e0_0;
//wire		Rclk3e0_1=rclk3e0_1;
//wire		Rclk3e0_2=rclk3e0_2;
//wire		Rclk3e0_3=rclk3e0_3;

wire	[7:0]	ErrorCnt3e0_0;
wire	[7:0]	ErrorCnt3e0_1;
wire	[7:0]	ErrorCnt3e0_2;
wire	[7:0]	ErrorCnt3e0_3;


prbs_quad prbs_quad_3e0(

    .Reset_n(reset_n) ,
    .Tclk(Tclk3e0) ,
    .Rclk_0(rclk3e0_0) ,
    .Rclk_1(rclk3e0_1) ,
    .Rclk_2(rclk3e0_2) ,
    .Rclk_3(rclk3e0_3) ,
    .Enable(sw_enable_3e0) ,
    .D_In_0(D_In_3e0_0) ,
    .D_In_1(D_In_3e0_1) ,
    .D_In_2(D_In_3e0_2) ,
    .D_In_3(D_In_3e0_3) ,
    .Err_Inj(sw_inj_err_3e0) ,
    .D_Out(D_Out3e0) ,
    .Error_0(Error3e0_0) ,
    .Error_1(Error3e0_1) ,
    .Error_2(Error3e0_2) ,
    .Error_3(Error3e0_3) ,
    .ErrorCnt_0(ErrorCnt3e0_0) ,
    .ErrorCnt_1(ErrorCnt3e0_1) ,
    .ErrorCnt_2(ErrorCnt3e0_2) ,
    .ErrorCnt_3(ErrorCnt3e0_3) ,
    .ClearErrorCnt(sw_clear_err_3e0) ,          
    .SelPRBS31(sw_select_prbs_31_3e0)   	
          );     





sw_ctrlstat sw_ctrlstat_i (
    .clk(usi_clk),
    .rstn(usi_rst_n),

    .usi_rdata(usi_rdata),
    .usi_ack(usi_ack),
    .usi_wdata(usi_wdata),
    .usi_addr(usi_addr),
    .usi_rdy(usi_rdy),
    .usi_wr_n(usi_wr_n),

    .rev_id(8'd4),
    
    .inj_err_360(sw_inj_err_360),
    .enable_360(sw_enable_360),
    .clear_err_360(sw_clear_err_360),
    .select_prbs_31_360(sw_select_prbs_31_360),
    .ErrorCnt360_0(ErrorCnt360_0),
    .ErrorCnt360_1(ErrorCnt360_1),
    .ErrorCnt360_2(ErrorCnt360_2),
    .ErrorCnt360_3(ErrorCnt360_3),
    
    .inj_err_3e0(sw_inj_err_3e0),
    .enable_3e0(sw_enable_3e0),
    .clear_err_3e0(sw_clear_err_3e0),
    .select_prbs_31_3e0(sw_select_prbs_31_3e0),
    .ErrorCnt3e0_0(ErrorCnt3e0_0),
    .ErrorCnt3e0_1(ErrorCnt3e0_1),
    .ErrorCnt3e0_2(ErrorCnt3e0_2),
    .ErrorCnt3e0_3(ErrorCnt3e0_3)    
);    


	
endmodule