#define _circuit_name  PCS0

#define _channel_A_options "SERDES Only(10/20-bit)"

#define _channel_B_options "SERDES Only(10/20-bit)"

#define _channel_C_options "SERDES Only(10/20-bit)"

#define _channel_D_options "SERDES Only(10/20-bit)"

#define _channel_align_mode	None

#define _en_control_ports 0

#define _enable_system_bus 1

#define _ref_clock_select "refclk"

#define _rate_mode "full_rate"

#define _refclk_mode 01

#define _20_bit_ch_a 0

#define _20_bit_ch_b 0

#define _20_bit_ch_c 0

#define _20_bit_ch_d 0

#define _maxrate 3.125

#define _lang verilog

#include <pcs/PCS.v>
