`timescale 1ns / 100 ps

module softreg_r (address, usi_addr, rdy, wr_n, rdata, rdata_par, data);

input [17:0] address;
input        rdy;
input        wr_n;
input [17:0] usi_addr;
input [7:0]  data;
output [7:0] rdata;
output       rdata_par;

reg  [7:0]  rdata; 
reg         rdata_par;

always @(usi_addr or address or wr_n or rdy or data)
begin
  if ((usi_addr == address) && ~wr_n && rdy)
  begin
    rdata <= data;
    rdata_par <= ~(data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7]);
  end
  else
  begin
    rdata <= 8'b00000000;
    rdata_par <= 1'b0;
  end
end

endmodule

/* --------------------------------------------------------------------------------------------------- */

//module softreg_rw (address, clk, reset_value, rstn, usi_addr, rdy, wr_n, wdata, rdata, rdata_par, data);
module softreg_rw (address, clk,  rstn, usi_addr, rdy, wr_n, wdata, rdata, rdata_par, data);

parameter reset_value= 8'h00;

input [17:0] address ;
input        clk ;
//input [7:0]  reset_value ;
input        rstn ;
input [17:0] usi_addr ;
input        rdy ;
input        wr_n ;
input [7:0]  wdata ;
output [7:0] rdata ;
output       rdata_par;
output [7:0] data ;

reg  [7:0]  rdata ;
reg  [7:0]  data_t ;
reg         rdata_par ; 


always @(usi_addr or address or wr_n or rdy or data_t)
begin
  // read
  if ((usi_addr == address) && ~wr_n && rdy)
  begin
    rdata <= data_t ;
    rdata_par <= ~(data_t[0] ^ data_t[1] ^ data_t[2] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[6] ^ data_t[7]) ;
  end
  else
  begin
    rdata <= 8'b00000000 ;
    rdata_par <= 1'b0 ;
  end
end


always @(negedge rstn or posedge clk)
begin
  if (~rstn)
    data_t <= reset_value ;
     
  // write
  else if ((usi_addr == address) && wr_n && rdy)
    data_t <= wdata;
end

assign data = data_t;

endmodule