`timescale 1ns /10ps

module prbs_quad (
    Reset_n           ,
    Tclk             ,
    Rclk_0             ,
    Rclk_1             ,
    Rclk_2             ,
    Rclk_3             ,
    Enable            ,
    D_In_0              ,
    D_In_1              ,
    D_In_2              ,
    D_In_3              ,
    Err_Inj           ,
    D_Out             ,
    Error_0             ,
    Error_1             ,
    Error_2             ,
    Error_3             ,
    ErrorCnt_0          ,
    ErrorCnt_1          ,
    ErrorCnt_2          ,
    ErrorCnt_3          ,
    ClearErrorCnt	,          
    SelPRBS31          
);

input Reset_n;
input Tclk;
input Rclk_0;
input Rclk_1;
input Rclk_2;
input Rclk_3;
input Enable;
input Err_Inj;
input ClearErrorCnt;
input SelPRBS31;

//DATA IN 
input [9:0]  D_In_0;
input [9:0]  D_In_1;
input [9:0]  D_In_2;
input [9:0]  D_In_3;

//DATA OUT 
output [9:0]  D_Out;
reg [9:0]  D_Out;



//Error 
output [7:0]  ErrorCnt_0;
output [7:0]  ErrorCnt_1;
output [7:0]  ErrorCnt_2;
output [7:0]  ErrorCnt_3;

reg [7:0]  ErrorCnt_0;
reg [7:0]  ErrorCnt_1;
reg [7:0]  ErrorCnt_2;
reg [7:0]  ErrorCnt_3;

//Error 
output  Error_0;
output  Error_1;
output  Error_2;
output  Error_3;

reg  Error_0;
reg  Error_1;
reg  Error_2;
reg  Error_3;


//DATA IN 
reg [9:0]  D_In_0_reg;
reg [9:0]  D_In_1_reg;
reg [9:0]  D_In_2_reg;
reg [9:0]  D_In_3_reg;


//pipeline
always @(negedge Reset_n or posedge Rclk_0)
	if (~Reset_n)
		D_In_0_reg <= #1 0;
	else	
		D_In_0_reg <= #1 D_In_0;

always @(negedge Reset_n or posedge Rclk_1)
	if (~Reset_n)
		D_In_1_reg <= #1 0;
	else	
		D_In_1_reg <= #1 D_In_1;
		
		
always @(negedge Reset_n or posedge Rclk_2)
	if (~Reset_n)
		D_In_2_reg <= #1 0;
	else	
		D_In_2_reg <= #1 D_In_2;


always @(negedge Reset_n or posedge Rclk_3)
	if (~Reset_n)
		D_In_3_reg <= #1 0;
	else	
		D_In_3_reg <= #1 D_In_3;


wire  [9:0] prbs_31_D_Out;

wire  prbs_31_Error_0;
wire  prbs_31_Error_1;
wire  prbs_31_Error_2;
wire  prbs_31_Error_3;

wire [7:0] prbs_31_ErrorCnt_0;
wire [7:0] prbs_31_ErrorCnt_1;
wire [7:0] prbs_31_ErrorCnt_2;
wire [7:0] prbs_31_ErrorCnt_3;

prbs_31_10bit_quad prbs_31_10bit_quad_i (
	.Reset_n(Reset_n) ,
	.Tclk(Tclk) ,
	.Rclk_0(Rclk_0) ,
	.Rclk_1(Rclk_1) ,
	.Rclk_2(Rclk_2) ,
	.Rclk_3(Rclk_3) ,
	.Enable(Enable) ,
	.D_In_0(D_In_0_reg) ,
	.D_In_1(D_In_1_reg) ,
	.D_In_2(D_In_2_reg) ,
	.D_In_3(D_In_3_reg) ,
	.Err_Inj(Err_Inj) ,
	.D_Out(prbs_31_D_Out) ,
	.Error_0(prbs_31_Error_0) ,
	.Error_1(prbs_31_Error_1) ,
	.Error_2(prbs_31_Error_2) ,
	.Error_3(prbs_31_Error_3) ,
	.ErrorCnt_0(prbs_31_ErrorCnt_0) ,
	.ErrorCnt_1(prbs_31_ErrorCnt_1) ,
	.ErrorCnt_2(prbs_31_ErrorCnt_2) ,
	.ErrorCnt_3(prbs_31_ErrorCnt_3) ,
	.ClearErrorCnt(ClearErrorCnt)    
);



wire  [9:0] prbs_7_D_Out;

wire  prbs_7_Error_0;
wire  prbs_7_Error_1;
wire  prbs_7_Error_2;
wire  prbs_7_Error_3;

wire [7:0] prbs_7_ErrorCnt_0;
wire [7:0] prbs_7_ErrorCnt_1;
wire [7:0] prbs_7_ErrorCnt_2;
wire [7:0] prbs_7_ErrorCnt_3;


prbs_7_10bit_quad prbs_7_10bit_quad_i (
	.Reset_n(Reset_n) ,
	.Tclk(Tclk) ,
	.Rclk_0(Rclk_0) ,
	.Rclk_1(Rclk_1) ,
	.Rclk_2(Rclk_2) ,
	.Rclk_3(Rclk_3) ,
	.Enable(Enable) ,
	.D_In_0(D_In_0_reg) ,
	.D_In_1(D_In_1_reg) ,
	.D_In_2(D_In_2_reg) ,
	.D_In_3(D_In_3_reg) ,
	.Err_Inj(Err_Inj) ,
	.D_Out(prbs_7_D_Out) ,
	.Error_0(prbs_7_Error_0) ,
	.Error_1(prbs_7_Error_1) ,
	.Error_2(prbs_7_Error_2) ,
	.Error_3(prbs_7_Error_3) ,
	.ErrorCnt_0(prbs_7_ErrorCnt_0) ,
	.ErrorCnt_1(prbs_7_ErrorCnt_1) ,
	.ErrorCnt_2(prbs_7_ErrorCnt_2) ,
	.ErrorCnt_3(prbs_7_ErrorCnt_3) ,
	.ClearErrorCnt(ClearErrorCnt)    
);


//Select DATA Output
always @(negedge Reset_n or posedge Tclk)
	if (~Reset_n)
		D_Out <= #1 0;

	else
		begin
		if (SelPRBS31)		
			D_Out <= #1 prbs_31_D_Out;

		else
			D_Out <= #1 prbs_7_D_Out;
		end	




//Select PRBS Error_0 Outputs
always @(negedge Reset_n or posedge Rclk_0)
	if (~Reset_n)
		begin
		ErrorCnt_0 <= #1 0;
		Error_0 <= #1 0;
		end
	else
		begin
		if (SelPRBS31)
			begin
			ErrorCnt_0 <= #1 prbs_31_ErrorCnt_0;
			Error_0 <= #1 prbs_31_Error_0;
			end			
		else
			begin
			ErrorCnt_0 <= #1 prbs_7_ErrorCnt_0;
			Error_0 <= #1 prbs_7_Error_0;
			end	
		end
		
//Select PRBS Error_1 Outputs
always @(negedge Reset_n or posedge Rclk_1)
	if (~Reset_n)
		begin
		ErrorCnt_1 <= #1 0;
		Error_1 <= #1 0;
		end
	else
		begin
		if (SelPRBS31)
			begin
			ErrorCnt_1 <= #1 prbs_31_ErrorCnt_1;
			Error_1 <= #1 prbs_31_Error_1;
			end			
		else
			begin
			ErrorCnt_1 <= #1 prbs_7_ErrorCnt_1;
			Error_1 <= #1 prbs_7_Error_1;
			end	
		end
		
//Select PRBS Error_2 Outputs
always @(negedge Reset_n or posedge Rclk_2)
	if (~Reset_n)
		begin
		ErrorCnt_2 <= #1 0;
		Error_2 <= #1 0;
		end
	else
		begin
		if (SelPRBS31)
			begin
			ErrorCnt_2 <= #1 prbs_31_ErrorCnt_2;
			Error_2 <= #1 prbs_31_Error_2;
			end			
		else
			begin
			ErrorCnt_2 <= #1 prbs_7_ErrorCnt_2;
			Error_2 <= #1 prbs_7_Error_2;
			end	
		end
		
//Select PRBS Error_3 Outputs
always @(negedge Reset_n or posedge Rclk_3)
	if (~Reset_n)
		begin
		ErrorCnt_3 <= #1 0;
		Error_3 <= #1 0;
		end
	else
		begin
		if (SelPRBS31)
			begin
			ErrorCnt_3 <= #1 prbs_31_ErrorCnt_3;
			Error_3 <= #1 prbs_31_Error_3;
			end			
		else
			begin
			ErrorCnt_3 <= #1 prbs_7_ErrorCnt_3;
			Error_3 <= #1 prbs_7_Error_3;
			end	
		end
		
			
endmodule
