`timescale 1ns/10ps

module cjpat_gen(

	//--- data/control output ---
	cjpat_gen_data_8b,
	cjpat_gen_ctl,

	//--- misc control ---
	tclk,
	sys_reset_z, 
	inj_err_n
          );      

//new stuff for programability

input  inj_err_n;


//--- data/control output ---
output	[7:0]	cjpat_gen_data_8b;
output		cjpat_gen_ctl;

//--- misc control ---
input		tclk;
input		sys_reset_z;	//system reset
//------------ end of I/O list --------------------------------------

//------------------------------------------------------------------------
// Parameters
//------------------------------------------------------------------------
parameter [8:0] RAMCOUNT = 9'd384;
//--------------------------------------------------------------------
// data generation logic
//--------------------------------------------------------------------
//--- increment data counters ---




reg     [8:0]	address;
wire    [9:0]	romdata;



ROM512X10 CJPATRAMTX 
	(.Address(address), 
	 .OutClock(tclk), 
	 .OutClockEn(1'b1), 
	 .Reset(1'b0), 
	 .Q(romdata)
	 );
	 
always @(posedge tclk or negedge sys_reset_z) 
    if (~sys_reset_z) 
	  address <= #1 0;

    else
    	begin
    	if (address ==  RAMCOUNT -1 )
    		address <= #1 0;
    	else
    		address <= #1 address +1;

	end
	
	
//--------------------------------------------------------------------
// error injection logic
//--------------------------------------------------------------------
reg     inj_err_n_1, inj_err_n_2, inj_err_n_3, senderror;
wire sendoneerror ;
assign sendoneerror = (~inj_err_n_2) & inj_err_n_3;


always @(posedge tclk or negedge sys_reset_z) 
    if (~sys_reset_z) 
	begin
	  inj_err_n_1 <= #1 1'b1;
	  inj_err_n_2 <= #1 1'b1;
	  inj_err_n_3 <= #1 1'b1;
	  senderror <= #1 1'b0;
  	end //if
    else 
	begin 
	inj_err_n_1 <= inj_err_n;
	inj_err_n_2 <= inj_err_n_1;
	inj_err_n_3 <= inj_err_n_2;
	if (sendoneerror)
		senderror <= #1 1'b1;
	else
		senderror <= #1 1'b0;
		
	end

//--------------------------------------------------------------------
// data generation logic
//--------------------------------------------------------------------

reg	[7:0]	cjpat_gen_data_8b;
reg		cjpat_gen_ctl;

reg	[7:0]	cjpat_gen_int_data_8b;
reg		cjpat_gen_int_ctl;

//--- load output data and control
always @(posedge tclk or negedge sys_reset_z) 
    if (~sys_reset_z) 
	begin
        cjpat_gen_data_8b[7:0] <= #1 8'd0;
        cjpat_gen_ctl <= #1 0;
        cjpat_gen_int_data_8b[7:0] <= #1 8'd0;
        cjpat_gen_int_ctl <= #1 0;
            	end //if

    else 
    	begin 
    		if (senderror)
    			begin
    			cjpat_gen_int_data_8b[7:0] <= #1 8'hEE;
        		cjpat_gen_int_ctl <=  #1 0;
        		end
        	else
        	    	begin
    			cjpat_gen_int_data_8b[7:0] <= #1 romdata[7:0];
        		cjpat_gen_int_ctl <=  #1 romdata[8];
        		end
        cjpat_gen_data_8b[7:0] <= #1 cjpat_gen_int_data_8b[7:0];
        cjpat_gen_ctl <=  #1 cjpat_gen_int_ctl;		
   
    	end //else

endmodule
