                    I2C Master with WISHBONE Reference Design
===============================================================================

File List (17 files)
 1. /RD1046/docs/rd1046.pdf		      --> I2C master with WISHBONE design document
    /RD1046/docs/rd1046_readme.txt            --> Read me file (this file)
    /RD1046/docs/I2C_Bus_specification.pdf    --> I2C spec version 2.1
 2. /RD1046/Project/xo/i2c_master_wb.syn      --> ispLEVER project file
    /RD1046/Project/xo/i2c_master_wb.lpf      --> preference file
    /RD1046/Project/xo/tst_bench_top_tff.udo  --> script for functional simulation
    /RD1046/Project/xo/tst_bench_top_tff.udo  --> script for timing simulation
 3. /RD1046/source/i2c_master_wb_top.v        --> source file - top level
    /RD1046/source/i2c_master_byte_ctrl.v     --> source file 
    /RD1046/source/i2c_master_bit_ctrl.v      --> source file 
    /RD1046/source/i2c_master_registers.v     --> source file 
    /RD1046/source/i2c_master_defines..v      --> source file 
 4. /RD1046/testbench/tst_bench_top.v         --> Testbench for simulation - top-level
    /RD1046/testbench/i2c_slave_model.v       --> Testbench for simulation
    /RD1046/testbench/wb_master_model.v       --> Testbench for simulation
    /RD1046/testbench/timescale.v             --> Testbench for simulation
    /RD1046/testbench/mem_init.txt            --> Memory initialization file for simulation
                                      
How to bring up the project:          
1. Unzip the RD1046_revyy.y.zip file using the existing folder names, where yy.y is the current
   version of the zip file            
2. Bring up ispLEVER Project Navigator  
3. In the File menu, click on Open Project, then browse to the directory where the 
   reference design is placed, select RD1046\Project\<device>\i2c_master_wb.syn and click Open
                                      
How to run simulation:                
1. In the Project Navigator, highlight the ..\..\testbench\tst_bench_top.v file on the left-side panel, 
   user will see 3 simulation options on the right panel
2. For functional simulation, double click on Verilog Functional Simulation with Aldec Active-HDL.
   Aldec simulator will be brought up, click yes to overwrite the existing file
3. Functional simulation will run until complete. user will see a script shown in the Console panel
   like this:
   
       status:                    0 Testbench started
    
       INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0)
       
       status:                 1000 done reset
       status:                13200 programmed registers
       status:                21200 verified registers
       status:                27200 core enabled
       status:                37200 generate 'start', write cmd 20 (slave address+write)
       status:             10339200 tip==0
       status:             10349200 write slave memory address 01
       status:             19427200 tip==0
       status:             19437200 write data a5
       status:             37933200 tip==0
       status:             37943200 write next data 5a, generate 'stop'
       status:             48029200 tip==0
       status:             48039200 generate 'start', write cmd 20 (slave address+write)
       status:             58335200 tip==0
       status:             58345200 write slave address 01
       status:             67423200 tip==0
       status:             67433200 generate 'repeated start', write cmd 21 (slave address+read)
       status:             77723200 tip==0
       status:             77729200 read + ack
       status:             86813200 tip==0
       status:             86819200 received a5
       status:             86825200 read + ack
       status:             95903200 tip==0
       status:             95909200 received 5a
       status:             95915200 read + nack
       status:            104993200 tip==0
       status:            104999200 received 11 from 3rd read address
       status:            105009200 generate 'start', write cmd 20 (slave address+write). Check invalid address
       status:            115299200 tip==0
       status:            115309200 write slave memory address 10
       status:            124387200 tip==0
       status:            124387200 Check for nack
       status:            124393200 generate 'stop'
       status:            124399200 tip==0
  
       status:            149399200 Testbench done
 
4. For timing simulation, double click on Verilog Post-Route Timing Simulation with Aldec Active-HDL. Similar 
   message will be shown in the console panel of the Aldec Active-HDL simulator. 

How to run Place and Route, JEDEC generation, and Timing Analysis:
1. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on 
   Place and Route Design. This will bring the design through synthesis, mapping, and place and route. 
2. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on 
   Generate Data File (JEDEC). This will generate the jedec file for the design. 
3. Once Place and Route is done, user can double click on Place and Route Trace Report on the right-side panel 
   to get the timing analysis result. 

