    Synthesis Report
    #Build: Synplify Pro F-2012.03L , Build 063R, May 17 2012
    #install: C:\Diamond\diamond\2.0\synpbase
    #OS: Windows XP 5.1
    #Hostname: L25531

    #Implementation: impl1

    $ Start of Compile
    #Tue Jul 24 16:13:37 2012

    Synopsys Verilog Compiler, version comp201203rcp1, Build 061R, built May 17 2012
    @N|Running in 32-bit mode
    Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @I::"C:\Diamond\diamond\2.0\synpbase\lib\lucent\machxo2.v"
    @I::"C:\Diamond\diamond\2.0\synpbase\lib\lucent\pmi_def.v"
    @I::"C:\Diamond\diamond\2.0\synpbase\lib\vlog\umr_capim.v"
    @I::"C:\Diamond\diamond\2.0\synpbase\lib\vlog\scemi_objects.v"
    @I::"C:\Diamond\diamond\2.0\synpbase\lib\vlog\scemi_pipes.svh"
    @I::"C:\Diamond\diamond\2.0\synpbase\lib\vlog\hypermods.v"
    @I::"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\pwm.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\LCDEncoding4to1.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcdencoding4to1com.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_registers.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_registers.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\..\testbench\timescale.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v"
    @N: CG334 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":161:12:161:24|Read directive translate_off
    @N: CG333 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":163:12:163:23|Read directive translate_on
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_defines.v"
    @N: CG346 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":394:38:394:46|Read full_case directive
    @N: CG347 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":394:48:394:60|Read parallel_case directive
    @N: CG346 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":398:40:398:48|Read full_case directive
    @N: CG347 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":398:50:398:62|Read parallel_case directive
    @W: CG286 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_bit_ctrl.v":398:17:398:20|Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_byte_ctrl.v"
    @N: CG334 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_byte_ctrl.v":106:12:106:24|Read directive translate_off
    @N: CG333 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_byte_ctrl.v":108:12:108:23|Read directive translate_on
    @N: CG346 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_byte_ctrl.v":275:34:275:42|Read full_case directive
    @N: CG347 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_byte_ctrl.v":275:44:275:56|Read parallel_case directive
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_wb_top.v"
    @N: CG334 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_wb_top.v":110:12:110:24|Read directive translate_off
    @N: CG333 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1046\source\i2c_master_wb_top.v":112:12:112:23|Read directive translate_on
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1044\Source\Spi_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\timescale.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\rom_ebr_wb.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\rom_ebr_wb.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\timescale.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\box_ave.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\sigmadelta_adc.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\adc_top.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\modem.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txcver_fifo.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txcver_fifo.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\system_conf.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver_fifo.v"
    @I:"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v":"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lm8_top.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_io_cntl.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_idec.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1043\source\lm8_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\led_sw_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\reset_gen.v"
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\reset_gen.v":60:4:60:11|rst1_out is already declared in this scope.
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\reset_gen.v":61:4:61:11|rst2_out is already declared in this scope.
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clk_switch.v"
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clk_switch.v":53:6:53:12|out_clk is already declared in this scope.
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clksource_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\debounce.v"
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\debounce.v":60:5:60:10|Pushed is already declared in this scope.
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\PowerCntr.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\ringosc.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v"
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":55:6:55:11|oscclk is already declared in this scope.
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":56:6:56:15|RingOSCraw is already declared in this scope.
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":59:5:59:19|CalbrateRingOSC is already declared in this scope.
    @W: CG921 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":66:5:66:14|RingOSCclk is already declared in this scope.
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\EFB_Module.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\BankController.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v"
    @I::"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\LCDCharMap.v"
    Verilog syntax check successful!
    File C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v changed - recompiling
    Selecting top level module Environment_Scanning
    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":557:7:557:11|Synthesizing module ILVDS

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1705:7:1705:12|Synthesizing module BCINRD

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\BankController.v":8:7:8:20|Synthesizing module BankController

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\reset_gen.v":46:7:46:15|Synthesizing module reset_gen

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\led_sw_wb.v":45:7:45:15|Synthesizing module lcd_sw_wb

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":46:7:46:18|Synthesizing module USBorBatt_wb

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\ringosc.v":46:7:46:13|Synthesizing module RingOSC

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\ringosc.v":56:12:56:26|No assignment to RingOSCEnbDelay
    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1793:7:1793:10|Synthesizing module OSCH

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":46:7:46:17|Synthesizing module oscclkclean

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clk_switch.v":44:7:44:16|Synthesizing module clk_switch

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clksource_wb.v":46:7:46:18|Synthesizing module clkselect_wb

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1043\source\lm8_wb.v":47:7:47:12|Synthesizing module lm8_wb

    	LM8_ADDR_W=32'b00000000000000000000000000011000
    	NUM_DECODE=32'b00000000000000000000000000000100
    	WB_ADDR_W=32'b00000000000000000000000000010100
    	NUM_SLAVES=32'b00000000000000000000000000010000
       Generated name = lm8_wb_24s_4s_20s_16s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_idec.v":40:7:40:15|Synthesizing module isp8_idec

    	PROM_AW=32'b00000000000000000000000000001011
       Generated name = isp8_idec_11s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v":135:7:135:16|Synthesizing module pmi_addsub

    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_result_width=32'b00000000000000000000000000001000
    	pmi_sign=24'b011011110110011001100110
    	pmi_family=24'b010110000100111100110010
    	module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010
       Generated name = pmi_addsub_8s_8s_off_XO2_pmi_addsub

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v":41:7:41:14|Synthesizing module isp8_alu

    	FAMILY_NAME=24'b010110000100111100110010
       Generated name = isp8_alu_XO2

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lm8_top.v":142:7:142:27|Synthesizing module pmi_distributed_spram

    	pmi_addr_depth=32'b00000000000000000000000000010000
    	pmi_addr_width=32'b00000000000000000000000000000100
    	pmi_data_width=32'b00000000000000000000000000001101
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
       Generated name = pmi_distributed_spram_16s_4s_13s_noreg_none_binary_XO2_pmi_distributed_spram_Z1

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":41:7:41:20|Synthesizing module isp8_flow_cntl

    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
    	PROM_AW=32'b00000000000000000000000000001011
    	FAMILY_NAME=24'b010110000100111100110010
       Generated name = isp8_flow_cntl_4s_16s_11s_XO2

    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":229:28:229:36|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":358:23:358:29|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":375:28:375:39|Removing redundant assignment
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_io_cntl.v":39:8:39:19|Synthesizing module isp8_io_cntl

    	PORT_AW=32'b00000000000000000000000000001000
       Generated name = isp8_io_cntl_8s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":513:7:513:13|Synthesizing module pmi_rom

    	pmi_addr_depth=32'b00000000000000000000100000000000
    	pmi_addr_width=32'b00000000000000000000000000001011
    	pmi_data_width=32'b00000000000000000000000000010010
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
    	pmi_resetmode=40'b0110000101110011011110010110111001100011
    	pmi_init_file=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	pmi_init_file_format=24'b011010000110010101111000
    	pmi_family=24'b010110000100111100110010
    	module_type=56'b01110000011011010110100101011111011100100110111101101101
       Generated name = pmi_rom_2048s_11s_18s_noreg_disable_async_prom_init.hex_hex_XO2_pmi_rom_Z2

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":42:7:42:15|Synthesizing module isp8_core

    	FAMILY_NAME=24'b010110000100111100110010
    	PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	PORT_AW=32'b00000000000000000000000000001000
    	EXT_AW=32'b00000000000000000000000000011000
    	PROM_AW=32'b00000000000000000000000000001011
    	PROM_AD=32'b00000000000000000000100000000000
    	REGISTERS_16=32'b00000000000000000000000000000000
    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
    	REG14=5'b01110
    	REG15=5'b01111
       Generated name = isp8_core_Z3

    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":337:28:337:36|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":349:28:349:36|Removing redundant assignment
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":488:7:488:27|Synthesizing module pmi_distributed_dpram

    	pmi_addr_depth=32'b00000000000000000000000000100000
    	pmi_addr_width=32'b00000000000000000000000000000101
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110110010001110000011100100110000101101101
       Generated name = pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lm8_top.v":142:7:142:27|Synthesizing module pmi_distributed_spram

    	pmi_addr_depth=32'b00000000000000000000000000100000
    	pmi_addr_width=32'b00000000000000000000000000000101
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
       Generated name = pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lm8_top.v":46:7:46:10|Synthesizing module isp8

    	FAMILY_NAME=24'b010110000100111100110010
    	PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	PORT_AW=32'b00000000000000000000000000001000
    	EXT_AW=32'b00000000000000000000000000011000
    	PROM_AW=32'b00000000000000000000000000001011
    	PROM_AD=32'b00000000000000000000100000000000
    	REGISTERS_16=32'b00000000000000000000000000000000
    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
       Generated name = isp8_XO2_prom_init.hex_8s_24s_11s_2048s_0s_4s_16s_Z6

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":51:7:51:13|Synthesizing module intface

    	CLK_IN_KHZ=32'b00000000000000000010111011100000
    	BAUD_RATE=32'b00000000000000011100001000000000
    	ADDRWIDTH=32'b00000000000000000000000000000011
    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	A_RBR=3'b000
    	A_THR=3'b000
    	A_IER=3'b001
    	A_IIR=3'b010
    	A_LCR=3'b011
    	A_LSR=3'b101
    	A_DIV=3'b111
    	A_MSR=5'b11000
    	A_MCR=5'b10000
    	idle=3'b000
    	int0=3'b001
    	int1=3'b010
    	int2=3'b011
    	int3=3'b100
       Generated name = intface_Z7

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":110:12:110:25|No assignment to wire fifo_empty_thr

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":158:27:158:34|No assignment to wire thr_fifo

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":187:7:187:25|No assignment to iir_rd_strobe_delay
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":191:7:191:12|No assignment to lsr2_r
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":191:15:191:20|No assignment to lsr3_r
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":191:23:191:28|No assignment to lsr4_r
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":210:15:210:34|No assignment to msr_rd_strobe_detect
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":214:16:214:28|No assignment to wire fifo_full_thr

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":216:16:216:35|No assignment to wire fifo_almost_full_thr

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":217:16:217:36|No assignment to wire fifo_almost_empty_thr

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":218:16:218:27|No assignment to wire fifo_din_thr

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":219:16:219:26|No assignment to fifo_wr_thr
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":220:16:220:28|No assignment to fifo_wr_q_thr
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":221:16:221:32|No assignment to wire fifo_wr_pulse_thr

    @W: CL113 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":355:4:355:9|Feedback mux created for signal mcr[1:0].
    @W: CL250 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":355:4:355:9|All reachable assignments to mcr[1:0] assign 0, register removed by optimization
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":49:7:49:12|Synthesizing module rxcver

    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	idle=3'b000
    	shift=3'b001
    	parity=3'b010
    	stop=3'b011
    	idle1=3'b100
    	lat_family=16'b0101100001001111
       Generated name = rxcver_8s_0s_0_1_2_3_4_XO

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|No assignment to wire rbr_fifo

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":96:27:96:36|No assignment to wire fifo_empty

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":97:27:97:42|No assignment to wire fifo_almost_full

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":106:25:106:29|No assignment to count
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":118:13:118:20|No assignment to rxclk_en
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":121:26:121:39|No assignment to wire rbr_fifo_error

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":135:16:135:24|No assignment to wire fifo_full

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":138:16:138:32|No assignment to wire fifo_almost_empty

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":139:16:139:23|No assignment to fifo_din
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":140:16:140:22|No assignment to fifo_wr
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":141:16:141:24|No assignment to fifo_wr_q
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":142:16:142:28|No assignment to wire fifo_wr_pulse

    @N: CL177 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":426:3:426:8|Sharing sequential element sin_d0_delay.
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":48:7:48:12|Synthesizing module txmitt

    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	start=3'b000
    	shift=3'b001
    	parity=3'b010
    	stop_1bit=3'b011
    	stop_2bit=3'b100
    	stop_halfbit=3'b101
    	start1=3'b110
       Generated name = txmitt_8s_0s_0_1_2_3_4_5_6

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":92:27:92:39|No assignment to tx_in_start_s
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":97:27:97:35|No assignment to txclk_ena
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":98:27:98:35|No assignment to txclk_enb
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":100:27:100:33|No assignment to count_v
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":101:27:101:36|No assignment to thr_rd_int
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":102:27:102:38|No assignment to thr_rd_delay
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":103:27:103:35|No assignment to last_word
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\modem.v":49:7:49:11|Synthesizing module modem

    	DATAWIDTH=32'b00000000000000000000000000001000
       Generated name = modem_8s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v":52:7:52:15|Synthesizing module uart_core

    	CLK_IN_KHZ=32'b00000000000000000010111011100000
    	BAUD_RATE=32'b00000000000000011100001000000000
    	ADDRWIDTH=32'b00000000000000000000000000000011
    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
       Generated name = uart_core_12000s_115200s_3s_8s_0s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\box_ave.v":66:7:66:13|Synthesizing module box_ave

    	ADC_WIDTH=32'b00000000000000000000000000001000
    	LPF_DEPTH_BITS=32'b00000000000000000000000000000011
       Generated name = box_ave_8s_3s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\sigmadelta_adc.v":62:7:62:20|Synthesizing module sigmadelta_adc

    	ADC_WIDTH=32'b00000000000000000000000000001000
    	ACCUM_BITS=32'b00000000000000000000000000001010
    	LPF_DEPTH_BITS=32'b00000000000000000000000000000011
       Generated name = sigmadelta_adc_8s_10s_3s

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1066\source\verilog\adc_top.v":62:7:62:13|Synthesizing module ADC_top

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v":45:7:45:12|Synthesizing module adc_wb

    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v":73:16:73:24|Removing redundant assignment
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v":53:19:53:21|No assignment to led
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":513:7:513:13|Synthesizing module pmi_rom

    	pmi_addr_depth=32'b00000000000000000000010000000000
    	pmi_addr_width=32'b00000000000000000000000000001010
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
    	pmi_resetmode=32'b01110011011110010110111001100011
    	pmi_init_file=64'b0110110101100101011011100111010100101110011010000110010101111000
    	pmi_init_file_format=24'b011010000110010101111000
    	pmi_family=24'b010110000100111100110010
    	module_type=56'b01110000011011010110100101011111011100100110111101101101
       Generated name = pmi_rom_1024s_10s_8s_noreg_disable_sync_menu.hex_hex_XO2_pmi_rom_Z8

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\rom_ebr_wb.v":45:7:45:16|Synthesizing module rom_ebr_wb

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1120:7:1120:9|Synthesizing module VHI

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":82:7:82:8|Synthesizing module BB

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1124:7:1124:9|Synthesizing module VLO

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1800:7:1800:9|Synthesizing module EFB

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\EFB_Module.v":8:7:8:16|Synthesizing module EFB_Module

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v":54:7:54:14|Synthesizing module capsense

    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v":209:17:209:24|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v":219:17:219:24|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v":229:17:229:24|Removing redundant assignment
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\capsense.v":239:17:239:24|Removing redundant assignment
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcdencoding4to1com.v":45:7:45:24|Synthesizing module LCDEncoding4to1com

    @W: CG296 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcdencoding4to1com.v":57:10:57:14|Incomplete sensitivity list - assuming completeness
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcdencoding4to1com.v":62:20:62:25|Referenced variable LCDcom is not in sensitivity list
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\pwm.v":45:7:45:9|Synthesizing module PWM

    @W: CG296 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\pwm.v":57:10:57:14|Incomplete sensitivity list - assuming completeness
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\pwm.v":62:4:62:5|Referenced variable Voltage is not in sensitivity list
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\LCDEncoding4to1.v":45:7:45:21|Synthesizing module LCDEncoding4to1

    @W: CG296 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\LCDEncoding4to1.v":59:10:59:14|Incomplete sensitivity list - assuming completeness
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\LCDEncoding4to1.v":65:20:65:30|Referenced variable LCDSegments is not in sensitivity list
    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v":43:7:43:15|Synthesizing module LCD4Digit

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\IPexpress\LCDCharMap.v":8:7:8:16|Synthesizing module LCDCharMap

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\debounce.v":44:7:44:26|Synthesizing module PushButton_Debouncer

    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\debounce.v":74:13:74:18|Removing redundant assignment
    @W: CL265 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\debounce.v":63:1:63:6|Pruning bit 29 of SampleReg[29:0] -- not in use ...

    @N: CG364 :"C:\Diamond\diamond\2.0\cae_library\synthesis\verilog\machxo2.v":1694:7:1694:11|Synthesizing module PCNTR

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\source\PowerCntr.v":8:7:8:15|Synthesizing module PowerCntr

    @N: CG364 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":46:7:46:26|Synthesizing module Environment_Scanning

    @W: CG296 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":713:10:713:17|Incomplete sensitivity list - assuming completeness
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":717:19:717:22|Referenced variable LCD1 is not in sensitivity list
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":721:19:721:22|Referenced variable LCD2 is not in sensitivity list
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":725:19:725:22|Referenced variable LCD3 is not in sensitivity list
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":718:15:718:26|Referenced variable CharSegments is not in sensitivity list
    @W: CG290 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":729:19:729:22|Referenced variable LCD4 is not in sensitivity list
    @N: CG179 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":753:19:753:30|Removing redundant assignment
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":363:9:363:15|Port-width mismatch for port adr_i. Formal has width 8, Actual 20
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":388:9:388:15|Port-width mismatch for port adr_i. Formal has width 8, Actual 20
    @W: CG781 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":482:0:482:8|Undriven input DCD_N on instance UART_INST, tying to 0
    @W: CG781 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":482:0:482:8|Undriven input CTS_N on instance UART_INST, tying to 0
    @W: CG781 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":482:0:482:8|Undriven input DSR_N on instance UART_INST, tying to 0
    @W: CG781 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":482:0:482:8|Undriven input RI_N on instance UART_INST, tying to 0
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":633:24:633:40|Port-width mismatch for port FastCounterSampleout. Formal has width 12, Actual 1
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":674:8:674:14|Port-width mismatch for port LCD1. Formal has width 8, Actual 7
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":675:8:675:14|Port-width mismatch for port LCD2. Formal has width 8, Actual 7
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":676:8:676:14|Port-width mismatch for port LCD3. Formal has width 8, Actual 7
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":677:8:677:14|Port-width mismatch for port LCD4. Formal has width 8, Actual 7
    @W: CS263 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":743:14:743:14|Port-width mismatch for port OutClockEn. Formal has width 1, Actual 32
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":154:6:154:16|No assignment to wire uart_rx_sig

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":184:12:184:24|No assignment to wire data_from_spi

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":186:6:186:12|No assignment to wire spi_ack

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":189:12:189:25|No assignment to wire data_from_i2c2

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":191:6:191:13|No assignment to wire i2c2_ack

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":195:6:195:14|No assignment to wire timer_ack

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":197:12:197:26|No assignment to wire data_from_timer

    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":216:15:216:26|No assignment to FastCounter1
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":217:15:217:26|No assignment to FastCounter2
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":218:15:218:26|No assignment to FastCounter3
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":219:15:219:26|No assignment to FastCounter4
    @W: CG133 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":221:15:221:27|No assignment to SampleCounter
    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":223:10:223:24|No assignment to wire FastCounter1Enb

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":224:10:224:24|No assignment to wire FastCounter2Enb

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":225:10:225:24|No assignment to wire FastCounter3Enb

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":226:10:226:24|No assignment to wire FastCounter4Enb

    @W: CG360 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":228:10:228:24|No assignment to wire SampleCounterCO

    @W: CL169 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":274:1:274:6|Pruning register counter[15:0]

    @W: CL271 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":649:1:649:6|Pruning bits 15 to 13 of lcdcounter[15:0] -- not in use ...

    @W: CL118 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":715:2:715:5|Latch generated from always block for signal LCD4Seg[6:0]; possible missing assignment in an if or case statement.
    @W: CL118 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":715:2:715:5|Latch generated from always block for signal LCD3Seg[6:0]; possible missing assignment in an if or case statement.
    @W: CL118 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":715:2:715:5|Latch generated from always block for signal LCD2Seg[6:0]; possible missing assignment in an if or case statement.
    @W: CL118 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":715:2:715:5|Latch generated from always block for signal LCD1Seg[6:0]; possible missing assignment in an if or case statement.
    @A: CL282 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":749:1:749:6|Feedback mux created for signal lcdnextstate[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":878:1:878:6|Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":749:1:749:6|Trying to extract state machine for register lcdstate
    Extracted state machine for register lcdstate
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    @W: CL156 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":293:19:309:19|*Input wb_ack[15:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
    @W: CL156 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":313:19:329:19|*Input wb_dat_i[127:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
    @W: CL157 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\Environment_Scanning.v":81:8:81:15|*Output I2CAlert has undriven bits -- simulation mismatch possible.
    @W: CL247 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v":53:14:53:17|Input port bit 7 of LCD1[7:0] is unused

    @W: CL247 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v":54:14:54:17|Input port bit 7 of LCD2[7:0] is unused

    @W: CL247 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v":55:14:55:17|Input port bit 7 of LCD3[7:0] is unused

    @W: CL247 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcd4digit.v":56:14:56:17|Input port bit 7 of LCD4[7:0] is unused

    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\LCDEncoding4to1.v":110:1:110:6|Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\pwm.v":101:1:101:6|Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 3 reachable states with original encodings of:
       000
       001
       010
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\lcdencoding4to1com.v":100:1:100:6|Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @W: CL246 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v":48:14:48:18|Input port bits 7 to 1 of dat_i[7:0] are unused

    @A: CL153 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\adc_wb.v":53:19:53:21|*Unassigned bits of led[7:0] are referenced and tied to 0 -- simulation mismatch possible.
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\uart_core.v":112:22:112:31|Input UART_CTI_I is unused
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\modem.v":99:2:99:7|Trying to extract state machine for register msr_reg
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":275:3:275:8|Trying to extract state machine for register genblk2.genblk1.tx_state
    Extracted state machine for register genblk2.genblk1.tx_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\txmitt.v":79:27:79:40|Input fifo_empty_thr is unused
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":269:3:269:8|Trying to extract state machine for register cs_state
    Extracted state machine for register cs_state
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       100
    @W: CL157 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|*Output rbr_fifo has undriven bits -- simulation mismatch possible.
    @W: CL157 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":96:27:96:36|*Output fifo_empty has undriven bits -- simulation mismatch possible.
    @W: CL157 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\rxcver.v":97:27:97:42|*Output fifo_almost_full has undriven bits -- simulation mismatch possible.
    @N: CL201 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":579:3:579:8|Trying to extract state machine for register genblk13.cs_state
    Extracted state machine for register genblk13.cs_state
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       100
    @W: CL246 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":114:16:114:20|Input port bits 7 to 3 of adr_i[7:0] are unused

    @W: CL246 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":148:28:148:30|Input port bits 7 to 4 of msr[7:0] are unused

    @W: CL157 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":110:12:110:25|*Output fifo_empty_thr has undriven bits -- simulation mismatch possible.
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":119:17:119:21|Input sel_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":120:17:120:21|Input bte_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":122:25:122:32|Input rbr_fifo is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":111:12:111:21|Input fifo_empty is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":113:12:113:17|Input thr_rd is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\rd1042\source\intface.v":112:12:112:27|Input fifo_almost_full is unused
    @W: CL246 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v":45:17:45:21|Input port bits 13 to 2 of instr[17:0] are unused

    @W: CL246 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\clksource_wb.v":49:13:49:17|Input port bits 7 to 1 of dat_i[7:0] are unused

    @W: CL190 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":111:1:111:6|Optimizing register bit RingOSCmax[9] to a constant 0
    @W: CL260 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":111:1:111:6|Pruning register bit 9 of RingOSCmax[9:0]

    @W: CL190 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":128:1:128:6|Optimizing register bit RingOSCcnt[9] to a constant 0
    @W: CL260 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\oscclkclean.v":128:1:128:6|Pruning register bit 9 of RingOSCcnt[9:0]

    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":47:7:47:11|Input clk_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":48:7:48:11|Input rst_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":49:13:49:17|Input adr_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":50:13:50:17|Input dat_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":53:7:53:10|Input we_i is unused
    @W: CL159 :"C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\..\source\USBorBatt_wb.v":54:7:54:11|Input cyc_i is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Jul 24 16:13:38 2012

    ###########################################################]
    Premap Report

    Synopsys Lattice Technology Pre-mapping, Version maplat, Build 401R, Built May 25 2012 10:34:30
    Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
    Product Version F-2012.03L

    Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

    @L: C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\impl1\Environment_Scanning_impl1_scck.rpt
    Printing clock  summary report in "C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\impl1\Environment_Scanning_impl1_scck.rpt" file
    @N: MF249 |Running in 32-bit mode.
    @N: MF257 |Gated clock conversion enabled
    @N: MF546 |Generated clock conversion enabled

    Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

    Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

    Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 61MB)

    Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 63MB)

    Warning: Found 2 combinational loops!
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
    1) instance DebounceRingOSCb[16] (netlist:keepbuf), output net "DebounceRingOSCb[16]" in work.Environment_Scanning(verilog)
        net        DebounceRingOSCb[16]
    @W: BN241 |Unable to finish printing loop, loop close not found
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    2) instance RingOSCb[6] (netlist:keepbuf), output net "RingOSCb[6]" in work.RingOSC(verilog)
        net        clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    @W: BN241 |Unable to finish printing loop, loop close not found
    End of loops
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clk_switch.v":85:19:85:37|Net clkselect_wb_inst.clk appears to be an unidentified clock source. Assuming default frequency.
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":800:33:800:73|Net DebounceRingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency.
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":823:26:823:55|Net ToggleUSERSTDBY appears to be an unidentified clock source. Assuming default frequency.
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":63:25:63:50|Net clkselect_wb_inst.RingOSC_inst.RingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency.

    Clock Summary
    **************

    Start                                                 Requested     Requested     Clock                                                 Clock
    Clock                                                 Frequency     Period        Type                                                  Group
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                                1.0 MHz       1000.000      system                                                system_clkgroup
    Environment_Scanning|clk_USB                          1.0 MHz       1000.000      inferred                                              Inferred_clkgroup_0
    clkselect_wb|oscclk_inferred_clock                    1.0 MHz       1000.000      inferred                                              Inferred_clkgroup_1
    Environment_Scanning|lcdcounter_derived_clock[2]      1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdcounter_derived_clock[12]     1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[0]        1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[1]        1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[2]        1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[3]        1.0 MHz       1000.000      derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    ===========================================================================================================================================================

    @W: MT529 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":579:3:579:8|Found inferred clock Environment_Scanning|clk_USB which controls 134 sequential elements including UART_INST/u_intface/genblk13®cs_state[4:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W: MT529 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\reset_gen.v":63:0:63:5|Found inferred clock clkselect_wb|oscclk_inferred_clock which controls 381 sequential elements including reset_gen_inst/reset_counter[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

    syn_allowed_resources : blockrams=7  set on top level netlist Environment_Scanning

    Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Pre-mapping successful!

    At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 79MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Jul 24 16:13:40 2012

    ###########################################################]
    Map & Optimize Report

    Synopsys Lattice Technology Mapper, Version maplat, Build 401R, Built May 25 2012 10:34:30
    Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
    Product Version F-2012.03L

    Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

    @N: MF249 |Running in 32-bit mode.
    @N: MF257 |Gated clock conversion enabled
    @N: MF546 |Generated clock conversion enabled

    Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

    Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

    Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB)

    Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)

    @N: MF203 |Set autoconstraint_io

    Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB)

    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":110:12:110:25|Tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z7)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":97:27:97:42|Tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":96:27:96:36|Tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":89:26:89:33|Tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO)
    @W: MO111 :|Tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :|Tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_12000s_115200s_3s_8s_0s)
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":97:18:97:21|Tristate driver I2CAlert on net I2CAlert has its enable tied to GND (module Environment_Scanning)
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance u_modem.rin_d1 of view:PrimLib.dffs(prim) in hierarchy view:work.uart_core_12000s_115200s_3s_8s_0s(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":351:3:351:8|Removing sequential instance ie_flag of view:PrimLib.dffre(prim) in hierarchy view:work.isp8_flow_cntl_4s_16s_11s_XO2(verilog) because there are no references to its outputs
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.dsrn_d1,  because it is equivalent to instance UART_INST.u_modem.dcdn_d1
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.dcdn_d1,  because it is equivalent to instance UART_INST.u_modem.ctsn_d1

    Available hyper_sources - for debug and ip models
    	None Found

    Warning: Found 2 combinational loops!
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
    1) instance DebounceRingOSCb[16] (netlist:keepbuf), output net "DebounceRingOSCb[16]" in work.Environment_Scanning(verilog)
        net        DebounceRingOSCb[16]
    @W: BN241 |Unable to finish printing loop, loop close not found
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    2) instance RingOSC_inst.RingOSCb[6] (netlist:keepbuf), output net "RingOSC_inst.RingOSCb[6]" in work.clkselect_wb(verilog)
        net        clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    @W: BN241 |Unable to finish printing loop, loop close not found
    End of loops
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":800:33:800:73|Net DebounceRingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency.
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":823:26:823:55|Net ToggleUSERSTDBY appears to be an unidentified clock source. Assuming default frequency.
    @W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":63:25:63:50|Net clkselect_wb_inst.RingOSC_inst.RingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency.

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

    Encoding state machine state[2:0] (netlist:statemachine)
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine lcdstate[3:0] (netlist:statemachine)
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\reset_gen.v":63:0:63:5|Found counter in view:work.Environment_Scanning(verilog) inst reset_gen_inst.reset_counter[3:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clksource_wb.v":171:1:171:6|Found counter in view:work.clkselect_wb(verilog) inst RingOSCEnbDelay[4:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clksource_wb.v":153:1:153:6|Found counter in view:work.clkselect_wb(verilog) inst OSCEnbDelay[4:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\oscclkclean.v":128:1:128:6|Found counter in view:work.oscclkclean(verilog) inst RingOSCcnt[8:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\oscclkclean.v":111:1:111:6|Found counter in view:work.oscclkclean(verilog) inst CalRingOSCcnt[9:0]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[1],  because it is equivalent to instance UART_INST.u_modem.msr_reg[0]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[3],  because it is equivalent to instance UART_INST.u_modem.msr_reg[0]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[7],  because it is equivalent to instance UART_INST.u_modem.msr_reg[6]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[6],  because it is equivalent to instance UART_INST.u_modem.msr_reg[5]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing instance UART_INST.u_modem.msr_reg[5],  because it is equivalent to instance UART_INST.u_modem.msr_reg[4]
    Encoding state machine genblk13\.cs_state[4:0] (netlist:statemachine)
    original code -> new code
       000 -> 00001
       001 -> 00010
       010 -> 00100
       011 -> 01000
       100 -> 10000
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[15],  because it is equivalent to instance UART_INST.u_intface.divisor[14]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[14],  because it is equivalent to instance UART_INST.u_intface.divisor[13]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[13],  because it is equivalent to instance UART_INST.u_intface.divisor[12]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[12],  because it is equivalent to instance UART_INST.u_intface.divisor[11]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[11],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[9],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing instance UART_INST.u_intface.divisor[8],  because it is equivalent to instance UART_INST.u_intface.divisor[10]
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Removing sequential instance divisor[10] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.intface_Z7(verilog) because there are no references to its outputs
    @A: BN291 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":225:3:225:8|Boundary register divisor[10] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    Encoding state machine cs_state[4:0] (netlist:statemachine)
    original code -> new code
       000 -> 00001
       001 -> 00010
       010 -> 00100
       011 -> 01000
       100 -> 10000
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":269:3:269:8|Found counter in view:work.rxcver_8s_0s_0_1_2_3_4_XO(verilog) inst databit_recved_num[3:0]
    @N: MF179 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\rxcver.v":286:10:286:30|Found 16 bit by 16 bit '==' comparator, 'cs_state12'
    Encoding state machine genblk2\.genblk1\.tx_state[6:0] (netlist:statemachine)
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\txmitt.v":275:3:275:8|Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk2\.genblk1\.counter[15:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1066\source\verilog\sigmadelta_adc.v":124:0:124:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst sigma[9:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1066\source\verilog\sigmadelta_adc.v":172:0:172:5|Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst counter[9:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\capsense.v":184:1:184:6|Found counter in view:work.capsense(verilog) inst SampleCounter[7:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\capsense.v":152:1:152:6|Found counter in view:work.capsense(verilog) inst FastCounter4[6:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\capsense.v":152:1:152:6|Found counter in view:work.capsense(verilog) inst FastCounter3[6:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\capsense.v":152:1:152:6|Found counter in view:work.capsense(verilog) inst FastCounter2[6:0]
    @N:"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\capsense.v":152:1:152:6|Found counter in view:work.capsense(verilog) inst FastCounter1[6:0]
    Encoding state machine state[7:0] (netlist:statemachine)
    original code -> new code
       000 -> 000
       001 -> 001
       010 -> 010
       011 -> 011
       100 -> 100
       101 -> 101
       110 -> 110
       111 -> 111
    Encoding state machine state[2:0] (netlist:statemachine)
    original code -> new code
       000 -> 00
       001 -> 01
       010 -> 10
    Encoding state machine state[7:0] (netlist:statemachine)
    original code -> new code
       000 -> 000
       001 -> 001
       010 -> 010
       011 -> 011
       100 -> 100
       101 -> 101
       110 -> 110
       111 -> 111
    Encoding state machine state[7:0] (netlist:statemachine)
    original code -> new code
       000 -> 000
       001 -> 001
       010 -> 010
       011 -> 011
       100 -> 100
       101 -> 101
       110 -> 110
       111 -> 111
    Encoding state machine state[7:0] (netlist:statemachine)
    original code -> new code
       000 -> 000
       001 -> 001
       010 -> 010
       011 -> 011
       100 -> 100
       101 -> 101
       110 -> 110
       111 -> 111
    Encoding state machine state[7:0] (netlist:statemachine)
    original code -> new code
       000 -> 000
       001 -> 001
       010 -> 010
       011 -> 011
       100 -> 100
       101 -> 101
       110 -> 110
       111 -> 111
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[0],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[0]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[1],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[1]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[2],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[2]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[3],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[3]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[4],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[4]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[5],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[5]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[6],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[6]
    @W: BN132 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":209:3:209:8|Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[7],  because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[7]
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1066\source\verilog\box_ave.v":108:0:108:5|Removing sequential instance adc_wb_inst.adc_inst.SSD_ADC.box_ave.result_valid of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\modem.v":99:2:99:7|Removing sequential instance UART_INST.u_modem.msr_reg[4] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[7] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[6] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[5] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[4] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[3] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":330:6:330:11|Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[2] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[3] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @A: BN291 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[3] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[2] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @A: BN291 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[1] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @A: BN291 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[1] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N: BN362 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[0] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.Environment_Scanning(verilog) because there are no references to its outputs
    @A: BN291 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":342:6:342:11|Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.

    Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

    @N: MF578 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":790:1:790:6|Incompatible asynchronous control logic preventing generated clock conversion of DebounceRingOSCen (netlist:FDCPE).

    #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

    ======================================================================================
                                    Instance:Pin        Generated Clock Optimization Status
    ======================================================================================
                           DebounceRingOSCen:C              Not Done
                                   USERSTDBY:C              Not Done
                              lcdcounter[12]:C              Not Done
                               lcdcounter[2]:C              Not Done
                              TimeOutStandby:C              Not Done
            PushButton_Debouncer_inst.Pushed:C              Not Done
         LCD4Digit_inst.LCD_12_inst.state[1]:C              Done
         LCD4Digit_inst.LCD_12_inst.state[0]:C              Done
      LCD4Digit_inst.LCD_12enc_inst.state[2]:C              Done
      LCD4Digit_inst.LCD_12enc_inst.state[1]:C              Done
      LCD4Digit_inst.LCD_12enc_inst.state[0]:C              Done
         LCD4Digit_inst.LCD_11_inst.state[1]:C              Done
         LCD4Digit_inst.LCD_11_inst.state[0]:C              Done
      LCD4Digit_inst.LCD_11enc_inst.state[2]:C              Done
      LCD4Digit_inst.LCD_11enc_inst.state[1]:C              Done
      LCD4Digit_inst.LCD_11enc_inst.state[0]:C              Done
         LCD4Digit_inst.LCD_10_inst.state[1]:C              Done
         LCD4Digit_inst.LCD_10_inst.state[0]:C              Done
      LCD4Digit_inst.LCD_10enc_inst.state[2]:C              Done
      LCD4Digit_inst.LCD_10enc_inst.state[1]:C              Done
      LCD4Digit_inst.LCD_10enc_inst.state[0]:C              Done
          LCD4Digit_inst.LCD_9_inst.state[1]:C              Done
          LCD4Digit_inst.LCD_9_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_9enc_inst.state[2]:C              Done
       LCD4Digit_inst.LCD_9enc_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_9enc_inst.state[0]:C              Done
          LCD4Digit_inst.LCD_8_inst.state[1]:C              Done
          LCD4Digit_inst.LCD_8_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_8enc_inst.state[2]:C              Done
       LCD4Digit_inst.LCD_8enc_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_8enc_inst.state[0]:C              Done
          LCD4Digit_inst.LCD_7_inst.state[1]:C              Done
          LCD4Digit_inst.LCD_7_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_7enc_inst.state[2]:C              Done
       LCD4Digit_inst.LCD_7enc_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_7enc_inst.state[0]:C              Done
          LCD4Digit_inst.LCD_6_inst.state[1]:C              Done
          LCD4Digit_inst.LCD_6_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_6enc_inst.state[2]:C              Done
       LCD4Digit_inst.LCD_6enc_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_6enc_inst.state[0]:C              Done
          LCD4Digit_inst.LCD_5_inst.state[1]:C              Done
          LCD4Digit_inst.LCD_5_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_5enc_inst.state[2]:C              Done
       LCD4Digit_inst.LCD_5enc_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_5enc_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_COM3_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_COM3_inst.state[0]:C              Done
    LCD4Digit_inst.LCD_COM3enc_inst.state[2]:C              Done
    LCD4Digit_inst.LCD_COM3enc_inst.state[1]:C              Done
    LCD4Digit_inst.LCD_COM3enc_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_COM2_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_COM2_inst.state[0]:C              Done
    LCD4Digit_inst.LCD_COM2enc_inst.state[2]:C              Done
    LCD4Digit_inst.LCD_COM2enc_inst.state[1]:C              Done
    LCD4Digit_inst.LCD_COM2enc_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_COM1_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_COM1_inst.state[0]:C              Done
    LCD4Digit_inst.LCD_COM1enc_inst.state[2]:C              Done
    LCD4Digit_inst.LCD_COM1enc_inst.state[1]:C              Done
    LCD4Digit_inst.LCD_COM1enc_inst.state[0]:C              Done
       LCD4Digit_inst.LCD_COM0_inst.state[1]:C              Done
       LCD4Digit_inst.LCD_COM0_inst.state[0]:C              Done
    LCD4Digit_inst.LCD_COM0enc_inst.state[2]:C              Done
    LCD4Digit_inst.LCD_COM0enc_inst.state[1]:C              Done
    LCD4Digit_inst.LCD_COM0enc_inst.state[0]:C              Done
          clkselect_wb_inst.OSCEnbDelay[4:0]:C              Not Done
                   clkselect_wb_inst.OSCEnb1:C              Not Done
    clkselect_wb_inst.clk_switch_inst1.capture2:C              Not Done
    clkselect_wb_inst.clk_switch_inst1.capture1:C              Not Done
    clkselect_wb_inst.clk_switch_inst1.transfer2:C              Not Done
    clkselect_wb_inst.clk_switch_inst1.transfer1:C              Not Done
    clkselect_wb_inst.oscclkclean_inst.RingOSCclk:C              Not Done

    ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 87MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 82MB peak: 87MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 87MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 87MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 82MB peak: 87MB)

    Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 83MB peak: 87MB)

    Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 99MB peak: 101MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 85MB peak: 101MB)

    @N: FX164 |The option to pack flops in the IOB has not been specified
    @W: MO111 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":81:8:81:15|Tristate driver I2CAlert_obuft.un1[0] on net I2CAlert has its enable tied to GND (module Environment_Scanning)
    @W: MO129 :|Sequential instance DebounceRingOSCen.res_reg_0 reduced to a combinational gate by constant propagation

    Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 86MB peak: 101MB)

    Writing Analyst data base C:\asdf\MachXO2 Pico Demo from Website\doc41117x92\Demo_MachXO2_Pico_Environment_Scanning\project\impl1\Environment_Scanning_impl1.srm

    Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 85MB peak: 101MB)

    Writing EDIF Netlist and constraint files
    F-2012.03L

    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 90MB peak: 101MB)

    Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 88MB peak: 101MB)

    ================= Gated clock report =================

    The following instances have NOT been converted
    Seq Inst                                              Instance Port     Clock                                          Reason for not converting
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    clkselect_wb_inst.oscclkclean_inst.IntOSCcnt[2]       CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.oscclkclean_inst.IntOSCcnt[1]       CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.oscclkclean_inst.IntOSCcnt[0]       CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.oscclkclean_inst.RingOSCcnten       CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.oscclkclean_inst.RingOSCcntstop     CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.clk_switch_inst1.capture2           CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.clk_switch_inst1.transfer2          CK                clkselect_wb_inst.oscclk                       Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    clkselect_wb_inst.OSCEnb1                             CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.OSCEnbDelay[4]                      CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.OSCEnbDelay[3]                      CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.OSCEnbDelay[2]                      CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.OSCEnbDelay[1]                      CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.OSCEnbDelay[0]                      CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnb1                         CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnbDelay[4]                  CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnbDelay[3]                  CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnbDelay[2]                  CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnbDelay[1]                  CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    clkselect_wb_inst.RingOSCEnbDelay[0]                  CK                clkselect_wb_inst.clk_switch_inst1.clk_clk     Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    LCD4Digit_inst.LCD_COM0enc_inst.state[2]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM0enc_inst.state[1]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM0enc_inst.state[0]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM0_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM0_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM1enc_inst.state[2]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM1enc_inst.state[1]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM1enc_inst.state[0]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM1_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM1_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM2enc_inst.state[2]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM2enc_inst.state[1]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM2enc_inst.state[0]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM2_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM2_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM3enc_inst.state[2]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM3enc_inst.state[1]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM3enc_inst.state[0]              CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM3_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_COM3_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_5enc_inst.state[2]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_5enc_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_5enc_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_5_inst.state[1]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_5_inst.state[0]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_6enc_inst.state[2]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_6enc_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_6enc_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_6_inst.state[1]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_6_inst.state[0]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_7enc_inst.state[2]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_7enc_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_7enc_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_7_inst.state[1]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_7_inst.state[0]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_8enc_inst.state[2]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_8enc_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_8enc_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_8_inst.state[1]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_8_inst.state[0]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_9enc_inst.state[2]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_9enc_inst.state[1]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_9enc_inst.state[0]                 CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_9_inst.state[1]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_9_inst.state[0]                    CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_10enc_inst.state[2]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_10enc_inst.state[1]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_10enc_inst.state[0]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_10_inst.state[1]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_10_inst.state[0]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_11enc_inst.state[2]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_11enc_inst.state[1]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_11enc_inst.state[0]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_11_inst.state[1]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_11_inst.state[0]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_12enc_inst.state[2]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_12enc_inst.state[1]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_12enc_inst.state[0]                CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_12_inst.state[1]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD4Digit_inst.LCD_12_inst.state[0]                   CK                lcdcountergen[2]                               Gated clock either has NO DRIVER or has MULTIPLE DRIVERS
    LCD1Seg[6]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[5]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[4]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[3]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[2]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[1]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD1Seg[0]                                            CK                lcdstate_225                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[6]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[5]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[4]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[3]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[2]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[1]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD2Seg[0]                                            CK                lcdstate_226                                   Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[6]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[5]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[4]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[3]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[2]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[1]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD3Seg[0]                                            CK                lcdstate[2]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[6]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[5]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[4]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[3]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[2]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[1]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    LCD4Seg[0]                                            CK                lcdstate[3]                                    Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements.
    USERSTDBY                                             CK                ToggleUSERSTDBY_i                              Gated clock does not have declared clock, add/enable clock constraint in SDC file.
    ======================================================================================================================================================================================================================================================

    ================= End gated clock report =================

    Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 88MB peak: 101MB)

    Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 88MB peak: 101MB)

    @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design

    Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 88MB peak: 101MB)

    Warning: Found 2 combinational loops!
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
    1) instance DebounceRingOSCb[16] (netlist:keepbuf), output net "DebounceRingOSCb[16]" in work.Environment_Scanning(verilog)
        net        DebounceRingOSCb[16]
    @W: BN241 |Unable to finish printing loop, loop close not found
    @W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    2) instance RingOSCb[6] (netlist:keepbuf), output net "RingOSCb[6]" in work.RingOSC(netlist)
        net        clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
    @W: BN241 |Unable to finish printing loop, loop close not found
    End of loops
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\powercntr.v":23:10:23:20|Blackbox PCNTR is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\ipexpress\efb_module.v":111:8:111:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\rom_ebr_wb.v":68:12:68:23|Blackbox pmi_rom_1024s_10s_8s_noreg_disable_sync_menu\.hex_hex_XO2_pmi_rom_Z8 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\lm8_top.v":130:21:130:33|Blackbox pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":434:33:434:45|Blackbox pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":320:15:320:26|Blackbox pmi_rom_2048s_11s_18s_noreg_disable_async_prom_init\.hex_hex_XO2_pmi_rom_Z2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v":394:30:394:43|Blackbox pmi_distributed_spram_16s_4s_13s_noreg_none_binary_XO2_pmi_distributed_spram_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v":95:18:95:27|Blackbox pmi_addsub_8s_8s_off_XO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clksource_wb.v":127:6:127:14|Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\source\ipexpress\bankcontroller.v":13:11:13:16|Blackbox BCINRD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT420 |Found inferred clock Environment_Scanning|clk_USB with period 1000.00ns. Please declare a user-defined clock on object "p:clk_USB"

    Found clock Environment_Scanning|lcdstate_derived_clock[3] with period 1000.00ns
    Found clock Environment_Scanning|lcdstate_derived_clock[2] with period 1000.00ns
    Found clock Environment_Scanning|lcdstate_derived_clock[1] with period 1000.00ns
    Found clock Environment_Scanning|lcdstate_derived_clock[0] with period 1000.00ns
    @W: MT420 |Found inferred clock clkselect_wb|oscclk_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:clkselect_wb_inst.oscclk"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Jul 24 16:13:45 2012
    #

    Top view:               Environment_Scanning
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        3
    Constraint File(s):
    @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    Performance Summary
    *******************

    Worst slack in design: 988.848

                                                       Requested     Estimated     Requested     Estimated                 Clock                                                 Clock
    Starting Clock                                     Frequency     Frequency     Period        Period        Slack       Type                                                  Group
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Environment_Scanning|clk_USB                       1.0 MHz       102.3 MHz     1000.000      9.774         990.226     inferred                                              Inferred_clkgroup_0
    Environment_Scanning|lcdstate_derived_clock[0]     1.0 MHz       104.2 MHz     1000.000      9.595         994.672     derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[1]     1.0 MHz       104.2 MHz     1000.000      9.595         994.672     derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[2]     1.0 MHz       104.2 MHz     1000.000      9.595         994.672     derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    Environment_Scanning|lcdstate_derived_clock[3]     1.0 MHz       104.2 MHz     1000.000      9.595         994.672     derived (from clkselect_wb|oscclk_inferred_clock)     Inferred_clkgroup_1
    clkselect_wb|oscclk_inferred_clock                 1.0 MHz       89.7 MHz      1000.000      11.152        988.848     inferred                                              Inferred_clkgroup_1
    System                                             1.0 MHz       116.3 MHz     1000.000      8.600         991.400     system                                                system_clkgroup
    ================================================================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                          |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                        Ending                                          |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                          System                                          |  1000.000    991.400  |  No paths    -      |  No paths    -      |  No paths    -
    System                                          Environment_Scanning|clk_USB                    |  1000.000    997.915  |  No paths    -      |  No paths    -      |  No paths    -
    System                                          clkselect_wb|oscclk_inferred_clock              |  1000.000    993.400  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|clk_USB                    System                                          |  1000.000    995.903  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|clk_USB                    Environment_Scanning|clk_USB                    |  1000.000    990.226  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|clk_USB                    clkselect_wb|oscclk_inferred_clock              |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              System                                          |  1000.000    992.622  |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              Environment_Scanning|clk_USB                    |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              clkselect_wb|oscclk_inferred_clock              |  1000.000    988.848  |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              Environment_Scanning|lcdstate_derived_clock[0]  |  1000.000    990.405  |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              Environment_Scanning|lcdstate_derived_clock[1]  |  1000.000    990.405  |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              Environment_Scanning|lcdstate_derived_clock[2]  |  1000.000    990.405  |  No paths    -      |  No paths    -      |  No paths    -
    clkselect_wb|oscclk_inferred_clock              Environment_Scanning|lcdstate_derived_clock[3]  |  1000.000    990.405  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|lcdstate_derived_clock[0]  System                                          |  1000.000    994.672  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|lcdstate_derived_clock[1]  System                                          |  1000.000    994.672  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|lcdstate_derived_clock[2]  System                                          |  1000.000    994.672  |  No paths    -      |  No paths    -      |  No paths    -
    Environment_Scanning|lcdstate_derived_clock[3]  System                                          |  1000.000    994.672  |  No paths    -      |  No paths    -      |  No paths    -
    ========================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    Input Ports:

    Port                  Starting            User           Arrival     Required
    Name                  Reference           Constraint     Time        Time         Slack
                          Clock
    -----------------------------------------------------------------------------------------
    Icc_analog_cmp_n      NA                  NA             NA          NA           NA
    Icc_analog_cmp_p      System (rising)     NA             0.000       997.660      997.660
    Icco_analog_cmp_n     NA                  NA             NA          NA           NA
    Icco_analog_cmp_p     System (rising)     NA             0.000       997.660      997.660
    PushBn                System (rising)     NA             0.000       994.722      994.722
    cap_btn1              System (rising)     NA             0.000       997.915      997.915
    cap_btn2              System (rising)     NA             0.000       997.915      997.915
    cap_btn3              System (rising)     NA             0.000       997.915      997.915
    cap_btn4              System (rising)     NA             0.000       997.915      997.915
    clk_USB               NA                  NA             NA          NA           NA
    rst                   System (rising)     NA             0.000       996.917      996.917
    scl                   System (rising)     NA             0.000       998.588      998.588
    sda                   System (rising)     NA             0.000       998.588      998.588
    spi_miso              System (rising)     NA             0.000       998.588      998.588
    uart_rx               System (rising)     NA             0.000       997.915      997.915
    =========================================================================================

    Output Ports:

    Port                Starting                                        User           Arrival     Required
    Name                Reference                                       Constraint     Time        Time         Slack
                        Clock
    -------------------------------------------------------------------------------------------------------------------
    EnAMP               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.189       1000.000     994.811
    EnTempSPI           clkselect_wb|oscclk_inferred_clock (rising)     NA             5.189       1000.000     994.811
    I2CAlert            NA                                              NA             NA          NA           NA
    Icc_analog_out      clkselect_wb|oscclk_inferred_clock (rising)     NA             5.052       1000.000     994.948
    Icco_analog_out     clkselect_wb|oscclk_inferred_clock (rising)     NA             5.052       1000.000     994.948
    LCD_5               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_6               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_7               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_8               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_9               clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_10              clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_11              clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_12              clkselect_wb|oscclk_inferred_clock (rising)     NA             5.504       1000.000     994.496
    LCD_COM0            clkselect_wb|oscclk_inferred_clock (rising)     NA             5.250       1000.000     994.750
    LCD_COM1            clkselect_wb|oscclk_inferred_clock (rising)     NA             4.682       1000.000     995.318
    LCD_COM2            clkselect_wb|oscclk_inferred_clock (rising)     NA             4.682       1000.000     995.318
    LCD_COM3            clkselect_wb|oscclk_inferred_clock (rising)     NA             5.250       1000.000     994.750
    cap_btn1            clkselect_wb|oscclk_inferred_clock (rising)     NA             3.775       1000.000     996.225
    cap_btn2            clkselect_wb|oscclk_inferred_clock (rising)     NA             3.775       1000.000     996.225
    cap_btn3            clkselect_wb|oscclk_inferred_clock (rising)     NA             3.775       1000.000     996.225
    cap_btn4            clkselect_wb|oscclk_inferred_clock (rising)     NA             3.775       1000.000     996.225
    scl                 System (rising)                                 NA             2.803       1000.000     997.197
    sda                 System (rising)                                 NA             2.803       1000.000     997.197
    spi_csn             System (rising)                                 NA             2.676       1000.000     997.324
    spi_mosi            System (rising)                                 NA             2.803       1000.000     997.197
    spi_sclk            System (rising)                                 NA             2.803       1000.000     997.197
    uart_tx             Environment_Scanning|clk_USB (rising)           NA             4.097       1000.000     995.903
    ===================================================================================================================

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report
    Part: lcmxo2_1200ze-3

    Register bits: 604 of 1280 (47%)
    Latch bits:      29
    PIC Latch:       0
    I/O cells:       34

    Details:
    BB:             9
    CCU2D:          181
    DP8KC:          1
    FD1P3AX:        37
    FD1P3BX:        35
    FD1P3DX:        282
    FD1S1AY:        28
    FD1S1D:         1
    FD1S3AX:        31
    FD1S3BX:        11
    FD1S3DX:        191
    FD1S3IX:        9
    FD1S3JX:        2
    GSR:            1
    IB:             4
    IFS1P3DX:       2
    ILVDS:          2
    INV:            41
    OB:             1
    OBZ:            18
    OFS1P3BX:       4
    ORCALUT4:       697
    PFUMX:          18
    PUR:            1
    VHI:            1
    VLO:            1
    false:          54
    true:           54
    Mapper successful!

    At Mapper Exit (Time elapsed 0h:00m:04s; Memory used current: 32MB peak: 101MB)

    Process took 0h:00m:05s realtime, 0h:00m:04s cputime
    # Tue Jul 24 16:13:45 2012

    ###########################################################]