@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":266:21:266:36|Found combinational loop during mapping at net DebounceRingOSCb[16]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: BN137 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":58:21:58:28|Found combinational loop during mapping at net clkselect_wb_inst.RingOSC_inst.RingOSCb[6]
@W: BN241 |Unable to finish printing loop, loop close not found
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\clk_switch.v":85:19:85:37|Net clkselect_wb_inst.clk appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":800:33:800:73|Net DebounceRingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\environment_scanning.v":823:26:823:55|Net ToggleUSERSTDBY appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\ringosc.v":63:25:63:50|Net clkselect_wb_inst.RingOSC_inst.RingOSCb_1[1] appears to be an unidentified clock source. Assuming default frequency. 
@W: MT529 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\rd1042\source\intface.v":579:3:579:8|Found inferred clock Environment_Scanning|clk_USB which controls 134 sequential elements including UART_INST/u_intface/genblk13Ūcs_state[4:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\asdf\machxo2 pico demo from website\doc41117x92\demo_machxo2_pico_environment_scanning\project\..\source\reset_gen.v":63:0:63:5|Found inferred clock clkselect_wb|oscclk_inferred_clock which controls 381 sequential elements including reset_gen_inst/reset_counter[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
