`

    #Build: Synplify Pro E-2010.09L-SP2 Beta, Build 077R, Jan 11 2011
    #install: C:\Diamond\diamond\1.2\synpbase
    #OS: Windows XP 5.1
    #Hostname: L25531

    #Implementation: impl1

    #Sat Feb 19 18:34:00 2011

    $ Start of Compile
    #Sat Feb 19 18:34:00 2011

    Synopsys Verilog Compiler, version comp520rcp2, Build 098R, built Jan 17 2011
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

    @I::"C:\Diamond\diamond\1.2\synpbase\lib\lucent\machxo2.v"
    @I::"C:\Diamond\diamond\1.2\synpbase\lib\vlog\hypermods.v"
    @I::"C:\Diamond\diamond\1.2\cae_library\synthesis\verilog\machxo2.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\audio_buffer.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\audio_buffer.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\timescale.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\clk_gen.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\wave_read.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\pwm.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\LCDEncoding4to1.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\lcdencoding4to1com.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\IPexpress\EFB_Module.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\uptime_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_registers.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_registers.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\..\testbench\timescale.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_bit_ctrl.v"
    @N:CG334 : i2c_master_bit_ctrl.v(161) | Read directive translate_off
    @N:CG333 : i2c_master_bit_ctrl.v(163) | Read directive translate_on
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_bit_ctrl.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_defines.v"
    @N:CG346 : i2c_master_bit_ctrl.v(394) | Read full_case directive
    @N:CG347 : i2c_master_bit_ctrl.v(394) | Read parallel_case directive
    @N:CG346 : i2c_master_bit_ctrl.v(398) | Read full_case directive
    @N:CG347 : i2c_master_bit_ctrl.v(398) | Read parallel_case directive
    @W:CG286 : i2c_master_bit_ctrl.v(398) | Case statement has both a full_case directive and a default clause.  The full_case directive is ignored.
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_byte_ctrl.v"
    @N:CG334 : i2c_master_byte_ctrl.v(106) | Read directive translate_off
    @N:CG333 : i2c_master_byte_ctrl.v(108) | Read directive translate_on
    @N:CG346 : i2c_master_byte_ctrl.v(275) | Read full_case directive
    @N:CG347 : i2c_master_byte_ctrl.v(275) | Read parallel_case directive
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1046\source\i2c_master_wb_top.v"
    @N:CG334 : i2c_master_wb_top.v(110) | Read directive translate_off
    @N:CG333 : i2c_master_wb_top.v(112) | Read directive translate_on
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1044\Source\Spi_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_core.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_core.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\timescale.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\rom_ebr_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\IPexpress\PLL.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\pll_soft_wb.v"
    @W:CG921 : pll_soft_wb.v(59) | lock_pll is already declared in this scope.
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1066\source\verilog\box_ave.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1066\source\verilog\sigmadelta_adc.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1066\source\verilog\adc_top.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\adc_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\modem.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\uart_core.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\uart_core.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\intface.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\intface.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\txcver_fifo.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\txcver_fifo.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\system_conf.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\uart_core.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\rxcver.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\rxcver.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\rxcver_fifo.v"
    @I:"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\uart_core.v":"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1042\source\txmitt.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\lm8_top.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_io_cntl.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_flow_cntl.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_alu.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\latticemico8_v3_1_verilog\source\isp8_idec.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\rd1043\source\lm8_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\led_sw_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\reset_gen.v"
    @W:CG921 : reset_gen.v(60) | rst1_out is already declared in this scope.
    @W:CG921 : reset_gen.v(61) | rst2_out is already declared in this scope.
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\clk_switch.v"
    @W:CG921 : clk_switch.v(10) | out_clk is already declared in this scope.
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\clksource_wb.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\debounce.v"
    @W:CG921 : debounce.v(17) | Pushed is already declared in this scope.
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\lcd4digit.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\source\PowerCntr.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\control_soc_demo.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\ringosc.v"
    @I::"C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\..\source\oscclkclean.v"
    @W:CG921 : oscclkclean.v(55) | oscclk is already declared in this scope.
    @W:CG921 : oscclkclean.v(56) | RingOSCraw is already declared in this scope.
    @W:CG921 : oscclkclean.v(59) | CalbrateRingOSC is already declared in this scope.
    @W:CG921 : oscclkclean.v(66) | RingOSCclk is already declared in this scope.
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module control_soc_demo
    @N:CG364 : machxo2.v(557) | Synthesizing module ILVDS

    @N:CG364 : reset_gen.v(46) | Synthesizing module reset_gen

    @N:CG364 : led_sw_wb.v(46) | Synthesizing module lcd_sw_wb

    @N:CG364 : ringosc.v(46) | Synthesizing module RingOSC

    @W:CG133 : ringosc.v(56) | No assignment to RingOSCEnbDelay
    @N:CG364 : machxo2.v(1802) | Synthesizing module OSCH

    @N:CG364 : oscclkclean.v(46) | Synthesizing module oscclkclean

    @N:CG364 : clk_switch.v(1) | Synthesizing module clk_switch

    @N:CG364 : clksource_wb.v(46) | Synthesizing module clkselect_wb

    @W:CL169 : clksource_wb.v(152) | Pruning Register OSCEnbDelay[4:0]

    @W:CL169 : clksource_wb.v(152) | Pruning Register OSCEnb1

    @N:CG364 : lm8_wb.v(47) | Synthesizing module lm8_wb

    	LM8_ADDR_W=32'b00000000000000000000000000011000
    	NUM_DECODE=32'b00000000000000000000000000000100
    	WB_ADDR_W=32'b00000000000000000000000000010100
    	NUM_SLAVES=32'b00000000000000000000000000010000
       Generated name = lm8_wb_24s_4s_20s_16s

    @N:CG364 : isp8_idec.v(40) | Synthesizing module isp8_idec

    	PROM_AW=32'b00000000000000000000000000001011
       Generated name = isp8_idec_11s

    @N:CG364 : isp8_alu.v(135) | Synthesizing module pmi_addsub

    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_result_width=32'b00000000000000000000000000001000
    	pmi_sign=24'b011011110110011001100110
    	pmi_family=24'b010110000100111100110010
    	module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010
       Generated name = pmi_addsub_8s_8s_off_XO2_pmi_addsub

    @N:CG364 : isp8_alu.v(41) | Synthesizing module isp8_alu

    	FAMILY_NAME=24'b010110000100111100110010
       Generated name = isp8_alu_XO2

    @N:CG364 : lm8_top.v(142) | Synthesizing module pmi_distributed_spram

    	pmi_addr_depth=32'b00000000000000000000000000010000
    	pmi_addr_width=32'b00000000000000000000000000000100
    	pmi_data_width=32'b00000000000000000000000000001101
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
       Generated name = pmi_distributed_spram_16s_4s_13s_noreg_none_binary_XO2_pmi_distributed_spram_Z1

    @N:CG364 : isp8_flow_cntl.v(41) | Synthesizing module isp8_flow_cntl

    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
    	PROM_AW=32'b00000000000000000000000000001011
    	FAMILY_NAME=24'b010110000100111100110010
       Generated name = isp8_flow_cntl_4s_16s_11s_XO2

    @N:CG179 : isp8_flow_cntl.v(229) | Removing redundant assignment
    @N:CG179 : isp8_flow_cntl.v(358) | Removing redundant assignment
    @N:CG179 : isp8_flow_cntl.v(375) | Removing redundant assignment
    @N:CG364 : isp8_io_cntl.v(39) | Synthesizing module isp8_io_cntl

    	PORT_AW=32'b00000000000000000000000000001000
       Generated name = isp8_io_cntl_8s

    @N:CG364 : isp8_core.v(513) | Synthesizing module pmi_rom

    	pmi_addr_depth=32'b00000000000000000000100000000000
    	pmi_addr_width=32'b00000000000000000000000000001011
    	pmi_data_width=32'b00000000000000000000000000010010
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
    	pmi_resetmode=40'b0110000101110011011110010110111001100011
    	pmi_init_file=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	pmi_init_file_format=24'b011010000110010101111000
    	pmi_family=24'b010110000100111100110010
    	module_type=56'b01110000011011010110100101011111011100100110111101101101
       Generated name = pmi_rom_2048s_11s_18s_noreg_disable_async_prom_init.hex_hex_XO2_pmi_rom_Z2

    @N:CG364 : isp8_core.v(42) | Synthesizing module isp8_core

    	FAMILY_NAME=24'b010110000100111100110010
    	PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	PORT_AW=32'b00000000000000000000000000001000
    	EXT_AW=32'b00000000000000000000000000011000
    	PROM_AW=32'b00000000000000000000000000001011
    	PROM_AD=32'b00000000000000000000100000000000
    	REGISTERS_16=32'b00000000000000000000000000000000
    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
    	REG14=5'b01110
    	REG15=5'b01111
       Generated name = isp8_core_Z3

    @N:CG179 : isp8_core.v(337) | Removing redundant assignment
    @N:CG179 : isp8_core.v(349) | Removing redundant assignment
    @N:CG364 : isp8_core.v(488) | Synthesizing module pmi_distributed_dpram

    	pmi_addr_depth=32'b00000000000000000000000000100000
    	pmi_addr_width=32'b00000000000000000000000000000101
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110110010001110000011100100110000101101101
       Generated name = pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4

    @N:CG364 : lm8_top.v(142) | Synthesizing module pmi_distributed_spram

    	pmi_addr_depth=32'b00000000000000000000000000100000
    	pmi_addr_width=32'b00000000000000000000000000000101
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_init_file=32'b01101110011011110110111001100101
    	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
    	pmi_family=24'b010110000100111100110010
    	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
       Generated name = pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5

    @N:CG364 : lm8_top.v(46) | Synthesizing module isp8

    	FAMILY_NAME=24'b010110000100111100110010
    	PROM_FILE=104'b01110000011100100110111101101101010111110110100101101110011010010111010000101110011010000110010101111000
    	PORT_AW=32'b00000000000000000000000000001000
    	EXT_AW=32'b00000000000000000000000000011000
    	PROM_AW=32'b00000000000000000000000000001011
    	PROM_AD=32'b00000000000000000000100000000000
    	REGISTERS_16=32'b00000000000000000000000000000000
    	PGM_STACK_AW=32'b00000000000000000000000000000100
    	PGM_STACK_AD=32'b00000000000000000000000000010000
       Generated name = isp8_XO2_prom_init.hex_8s_24s_11s_2048s_0s_4s_16s_Z6

    @N:CG364 : intface.v(51) | Synthesizing module intface

    	CLK_IN_MHZ=32'b00000000000000000000000000000010
    	BAUD_RATE=32'b00000000000000011100001000000000
    	ADDRWIDTH=32'b00000000000000000000000000000011
    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	A_RBR=3'b000
    	A_THR=3'b000
    	A_IER=3'b001
    	A_IIR=3'b010
    	A_LCR=3'b011
    	A_LSR=3'b101
    	A_DIV=3'b111
    	A_MSR=5'b11000
    	A_MCR=5'b10000
    	idle=3'b000
    	int0=3'b001
    	int1=3'b010
    	int2=3'b011
    	int3=3'b100
       Generated name = intface_Z7

    @W:CG360 : intface.v(108) | No assignment to wire fifo_empty_thr

    @W:CG360 : intface.v(156) | No assignment to wire thr_fifo

    @W:CG133 : intface.v(185) | No assignment to iir_rd_strobe_delay
    @W:CG133 : intface.v(189) | No assignment to lsr2_r
    @W:CG133 : intface.v(189) | No assignment to lsr3_r
    @W:CG133 : intface.v(189) | No assignment to lsr4_r
    @W:CG133 : intface.v(208) | No assignment to msr_rd_strobe_detect
    @W:CG360 : intface.v(212) | No assignment to wire fifo_full_thr

    @W:CG360 : intface.v(214) | No assignment to wire fifo_almost_full_thr

    @W:CG360 : intface.v(215) | No assignment to wire fifo_almost_empty_thr

    @W:CG360 : intface.v(216) | No assignment to wire fifo_din_thr

    @W:CG133 : intface.v(217) | No assignment to fifo_wr_thr
    @W:CG133 : intface.v(218) | No assignment to fifo_wr_q_thr
    @W:CG360 : intface.v(219) | No assignment to wire fifo_wr_pulse_thr

    @W:CL113 : intface.v(351) | Feedback mux created for signal mcr[1:0].
    @W:CL251 : intface.v(351) | All reachable assignments to mcr[1:0] assign 0, register removed by optimization
    @N:CG364 : rxcver.v(49) | Synthesizing module rxcver

    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	idle=3'b000
    	shift=3'b001
    	parity=3'b010
    	stop=3'b011
    	idle1=3'b100
    	lat_family=16'b0101100001001111
       Generated name = rxcver_8s_0s_0_1_2_3_4_XO

    @W:CG360 : rxcver.v(89) | No assignment to wire rbr_fifo

    @W:CG360 : rxcver.v(96) | No assignment to wire fifo_empty

    @W:CG360 : rxcver.v(97) | No assignment to wire fifo_almost_full

    @W:CG133 : rxcver.v(106) | No assignment to count
    @W:CG133 : rxcver.v(118) | No assignment to rxclk_en
    @W:CG360 : rxcver.v(121) | No assignment to wire rbr_fifo_error

    @W:CG360 : rxcver.v(135) | No assignment to wire fifo_full

    @W:CG360 : rxcver.v(138) | No assignment to wire fifo_almost_empty

    @W:CG133 : rxcver.v(139) | No assignment to fifo_din
    @W:CG133 : rxcver.v(140) | No assignment to fifo_wr
    @W:CG133 : rxcver.v(141) | No assignment to fifo_wr_q
    @W:CG360 : rxcver.v(142) | No assignment to wire fifo_wr_pulse

    @N:CL177 : rxcver.v(426) | Sharing sequential element sin_d0_delay.
    @N:CG364 : txmitt.v(48) | Synthesizing module txmitt

    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
    	start=3'b000
    	shift=3'b001
    	parity=3'b010
    	stop_1bit=3'b011
    	stop_2bit=3'b100
    	stop_halfbit=3'b101
    	start1=3'b110
       Generated name = txmitt_8s_0s_0_1_2_3_4_5_6

    @W:CG133 : txmitt.v(92) | No assignment to tx_in_start_s
    @W:CG133 : txmitt.v(97) | No assignment to txclk_ena
    @W:CG133 : txmitt.v(98) | No assignment to txclk_enb
    @W:CG133 : txmitt.v(100) | No assignment to count_v
    @W:CG133 : txmitt.v(101) | No assignment to thr_rd_int
    @W:CG133 : txmitt.v(102) | No assignment to thr_rd_delay
    @W:CG133 : txmitt.v(103) | No assignment to last_word
    @N:CG364 : modem.v(49) | Synthesizing module modem

    	DATAWIDTH=32'b00000000000000000000000000001000
       Generated name = modem_8s

    @N:CG364 : uart_core.v(52) | Synthesizing module uart_core

    	CLK_IN_MHZ=32'b00000000000000000000000000000010
    	BAUD_RATE=32'b00000000000000011100001000000000
    	ADDRWIDTH=32'b00000000000000000000000000000011
    	DATAWIDTH=32'b00000000000000000000000000001000
    	FIFO=32'b00000000000000000000000000000000
       Generated name = uart_core_2s_115200s_3s_8s_0s

    @N:CG364 : box_ave.v(66) | Synthesizing module box_ave

    	ADC_WIDTH=32'b00000000000000000000000000001000
    	LPF_DEPTH_BITS=32'b00000000000000000000000000000011
       Generated name = box_ave_8s_3s

    @N:CG364 : sigmadelta_adc.v(62) | Synthesizing module sigmadelta_adc

    	ADC_WIDTH=32'b00000000000000000000000000001000
    	ACCUM_BITS=32'b00000000000000000000000000001010
    	LPF_DEPTH_BITS=32'b00000000000000000000000000000011
       Generated name = sigmadelta_adc_8s_10s_3s

    @N:CG364 : adc_top.v(62) | Synthesizing module ADC_top

    @N:CG364 : adc_wb.v(46) | Synthesizing module adc_wb

    @N:CG179 : adc_wb.v(74) | Removing redundant assignment
    @W:CG133 : adc_wb.v(54) | No assignment to led
    @N:CG364 : isp8_core.v(513) | Synthesizing module pmi_rom

    	pmi_addr_depth=32'b00000000000000000000010000000000
    	pmi_addr_width=32'b00000000000000000000000000001010
    	pmi_data_width=32'b00000000000000000000000000001000
    	pmi_regmode=40'b0110111001101111011100100110010101100111
    	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
    	pmi_resetmode=32'b01110011011110010110111001100011
    	pmi_init_file=64'b0110110101100101011011100111010100101110011010000110010101111000
    	pmi_init_file_format=24'b011010000110010101111000
    	pmi_family=24'b010110000100111100110010
    	module_type=56'b01110000011011010110100101011111011100100110111101101101
       Generated name = pmi_rom_1024s_10s_8s_noreg_disable_sync_menu.hex_hex_XO2_pmi_rom_Z8

    @N:CG364 : rom_ebr_wb.v(45) | Synthesizing module rom_ebr_wb

    @N:CG364 : machxo2.v(1120) | Synthesizing module VHI

    @N:CG364 : machxo2.v(1124) | Synthesizing module VLO

    @N:CG364 : machxo2.v(1809) | Synthesizing module EFB

    @N:CG364 : EFB_Module.v(8) | Synthesizing module EFB_Module

    @N:CG364 : lcdencoding4to1com.v(2) | Synthesizing module LCDEncoding4to1com

    @W:CG296 : lcdencoding4to1com.v(14) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : lcdencoding4to1com.v(19) | Referenced variable LCDcom is not in sensitivity list
    @N:CG364 : pwm.v(2) | Synthesizing module PWM

    @W:CG296 : pwm.v(14) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : pwm.v(19) | Referenced variable Voltage is not in sensitivity list
    @N:CG364 : LCDEncoding4to1.v(2) | Synthesizing module LCDEncoding4to1

    @W:CG296 : LCDEncoding4to1.v(16) | Incomplete sensitivity list - assuming completeness
    @W:CG290 : LCDEncoding4to1.v(22) | Referenced variable LCDSegments is not in sensitivity list
    @N:CG364 : lcd4digit.v(1) | Synthesizing module LCD4Digit

    @N:CG364 : debounce.v(1) | Synthesizing module PushButton_Debouncer

    @N:CG179 : debounce.v(31) | Removing redundant assignment
    @W:CL265 : debounce.v(20) | Pruning bit 30 of SampleReg[30:0] - not in use ...

    @N:CG364 : machxo2.v(1703) | Synthesizing module PCNTR

    @N:CG364 : PowerCntr.v(8) | Synthesizing module PowerCntr

    @N:CG364 : control_soc_demo.v(45) | Synthesizing module control_soc_demo

    @W:CS149 : control_soc_demo.v(422) | Port width mismatch for port adr_i.  Formal has width 8, Actual 20
    @W:CG781 : control_soc_demo.v(531) | Undriven input DCD_N on instance UART_INST, tying to 0
    @W:CG781 : control_soc_demo.v(531) | Undriven input CTS_N on instance UART_INST, tying to 0
    @W:CG781 : control_soc_demo.v(531) | Undriven input DSR_N on instance UART_INST, tying to 0
    @W:CG781 : control_soc_demo.v(531) | Undriven input RI_N on instance UART_INST, tying to 0
    @W:CG781 : control_soc_demo.v(605) | Undriven input tc_ic on instance EFB_Inst, tying to 0
    @W:CS149 : control_soc_demo.v(808) | Port width mismatch for port LCD1.  Formal has width 8, Actual 7
    @W:CS149 : control_soc_demo.v(809) | Port width mismatch for port LCD2.  Formal has width 8, Actual 7
    @W:CS149 : control_soc_demo.v(810) | Port width mismatch for port LCD3.  Formal has width 8, Actual 7
    @W:CS149 : control_soc_demo.v(811) | Port width mismatch for port LCD4.  Formal has width 8, Actual 7
    @W:CG781 : control_soc_demo.v(993) | Undriven input CFGSTDBY on instance PowerCntr_inst, tying to 0
    @W:CG781 : control_soc_demo.v(994) | Undriven input CFGWAKE on instance PowerCntr_inst, tying to 0
    @W:CG360 : control_soc_demo.v(186) | No assignment to wire uart_rx_sig

    @W:CG360 : control_soc_demo.v(213) | No assignment to wire data_from_spi

    @W:CG360 : control_soc_demo.v(215) | No assignment to wire spi_ack

    @W:CG360 : control_soc_demo.v(218) | No assignment to wire data_from_i2c2

    @W:CG360 : control_soc_demo.v(220) | No assignment to wire i2c2_ack

    @W:CG360 : control_soc_demo.v(224) | No assignment to wire timer_ack

    @W:CG360 : control_soc_demo.v(226) | No assignment to wire data_from_timer

    @W:CG360 : control_soc_demo.v(229) | No assignment to wire clk_pll

    @W:CG360 : control_soc_demo.v(230) | No assignment to wire pll_status

    @W:CG360 : control_soc_demo.v(231) | No assignment to wire pll_ack

    @W:CG360 : control_soc_demo.v(278) | No assignment to wire LCD_COM0enc

    @W:CG360 : control_soc_demo.v(279) | No assignment to wire LCD_COM1enc

    @W:CG360 : control_soc_demo.v(280) | No assignment to wire LCD_COM2enc

    @W:CG360 : control_soc_demo.v(281) | No assignment to wire LCD_COM3enc

    @W:CG360 : control_soc_demo.v(282) | No assignment to wire LCD_5enc

    @W:CG360 : control_soc_demo.v(283) | No assignment to wire LCD_6enc

    @W:CG360 : control_soc_demo.v(284) | No assignment to wire LCD_7enc

    @W:CG360 : control_soc_demo.v(285) | No assignment to wire LCD_8enc

    @W:CG360 : control_soc_demo.v(286) | No assignment to wire LCD_9enc

    @W:CG360 : control_soc_demo.v(287) | No assignment to wire LCD_10enc

    @W:CG360 : control_soc_demo.v(288) | No assignment to wire LCD_11enc

    @W:CG360 : control_soc_demo.v(289) | No assignment to wire LCD_12enc

    @W:CG360 : control_soc_demo.v(291) | No assignment to wire LCDcom

    @W:CL169 : control_soc_demo.v(1032) | Pruning Register TimeOutStandby

    @W:CL169 : control_soc_demo.v(330) | Pruning Register counter[15:0]

    @W:CL265 : control_soc_demo.v(783) | Pruning bit 15 of lcdcounter[15:0] - not in use ...

    @W:CL265 : control_soc_demo.v(783) | Pruning bit 14 of lcdcounter[15:0] - not in use ...

    @W:CL265 : control_soc_demo.v(783) | Pruning bit 13 of lcdcounter[15:0] - not in use ...

    @N:CL201 : control_soc_demo.v(1032) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    @W:CL156 : control_soc_demo.v(352) | *Input wb_ack[15:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
    @W:CL156 : control_soc_demo.v(372) | *Input wb_dat_i[127:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(88) | *Output spi_sclk has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(89) | *Output spi_csn has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(90) | *Output spi_mosi has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(92) | *Output spi_miso has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(96) | *Output I2CAlert has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(97) | *Output scl has undriven bits - a simulation mismatch is possible
    @W:CL157 : control_soc_demo.v(98) | *Output sda has undriven bits - a simulation mismatch is possible
    @W:CL247 : lcd4digit.v(11) | Input port bit 7 of LCD1[7:0] is unused

    @W:CL247 : lcd4digit.v(12) | Input port bit 7 of LCD2[7:0] is unused

    @W:CL247 : lcd4digit.v(13) | Input port bit 7 of LCD3[7:0] is unused

    @W:CL247 : lcd4digit.v(14) | Input port bit 7 of LCD4[7:0] is unused

    @N:CL201 : LCDEncoding4to1.v(67) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @N:CL201 : pwm.v(58) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 3 reachable states with original encodings of:
       000
       001
       010
    @N:CL201 : lcdencoding4to1com.v(57) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @W:CL246 : adc_wb.v(49) | Input port bits 7 to 1 of dat_i[7:0] are unused

    @A:CL153 : adc_wb.v(54) | *Unassigned bits of led[7:0] have been referenced and are being tied to 0 - simulation mismatch possible
    @W:CL159 : uart_core.v(110) | Input UART_CTI_I is unused
    @N:CL201 : modem.v(99) | Trying to extract state machine for register msr_reg
    @N:CL201 : txmitt.v(275) | Trying to extract state machine for register genblk2.genblk1.tx_state
    Extracted state machine for register genblk2.genblk1.tx_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : txmitt.v(79) | Input fifo_empty_thr is unused
    @N:CL201 : rxcver.v(269) | Trying to extract state machine for register cs_state
    Extracted state machine for register cs_state
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       100
    @W:CL157 : rxcver.v(89) | *Output rbr_fifo has undriven bits - a simulation mismatch is possible
    @W:CL157 : rxcver.v(96) | *Output fifo_empty has undriven bits - a simulation mismatch is possible
    @W:CL157 : rxcver.v(97) | *Output fifo_almost_full has undriven bits - a simulation mismatch is possible
    @N:CL201 : intface.v(575) | Trying to extract state machine for register genblk13.cs_state
    Extracted state machine for register genblk13.cs_state
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       100
    @W:CL246 : intface.v(112) | Input port bits 7 to 3 of adr_i[7:0] are unused

    @W:CL246 : intface.v(146) | Input port bits 7 to 4 of msr[7:0] are unused

    @W:CL157 : intface.v(108) | *Output fifo_empty_thr has undriven bits - a simulation mismatch is possible
    @W:CL159 : intface.v(117) | Input sel_i is unused
    @W:CL159 : intface.v(118) | Input bte_i is unused
    @W:CL159 : intface.v(120) | Input rbr_fifo is unused
    @W:CL159 : intface.v(109) | Input fifo_empty is unused
    @W:CL159 : intface.v(111) | Input thr_rd is unused
    @W:CL159 : intface.v(110) | Input fifo_almost_full is unused
    @W:CL246 : isp8_alu.v(45) | Input port bits 13 to 2 of instr[17:0] are unused

    @W:CL246 : clksource_wb.v(49) | Input port bits 7 to 1 of dat_i[7:0] are unused

    @W:CL246 : led_sw_wb.v(50) | Input port bits 7 to 4 of dat_i[7:0] are unused

    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Sat Feb 19 18:34:01 2011

    ###########################################################]

`
Synopsys Lattice Technology Constraint Extraction, Version maplat, Build 040R, Built Jan 18 2011 10:48:50 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 Beta @N:MF249 : | Running in 32-bit mode. @N:MF257 : | Gated clock conversion enabled Warning: Found 2 combinational loops! @W:BN137 : control_soc_demo.v(322) | Found combinational loop during mapping at net DebounceRingOSCb[16] 1) instance work.control_soc_demo(verilog)-DebounceRingOSCb[16], output net "DebounceRingOSCb[16]" in work.control_soc_demo(verilog) @W:BN137 : ringosc.v(58) | Found combinational loop during mapping at net RingOSCb[6] 2) instance work.RingOSC(verilog)-RingOSCb[6], output net "RingOSCb[6]" in work.RingOSC(verilog) End of loops @W: : clk_switch.v(42) | Net clkselect_wb_inst/clk appears to be a clock source which was not identfied. Assuming default frequency. Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB) Timing Extraction successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Feb 19 18:34:01 2011 ###########################################################] Synopsys Lattice Technology Mapper, Version maplat, Build 040R, Built Jan 18 2011 10:48:50 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 Beta @N:MF249 : | Running in 32-bit mode. @N:MF257 : | Gated clock conversion enabled @W:MO111 : intface.v(108) | tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z7) @W:MO111 : rxcver.v(97) | tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(96) | tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : rxcver.v(89) | tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_XO) @W:MO111 : | tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : | tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_2s_115200s_3s_8s_0s) @W:MO111 : control_soc_demo.v(122) | tristate driver sda on net sda has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver scl on net scl has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver I2CAlert on net I2CAlert has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver spi_miso on net spi_miso has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver spi_mosi on net spi_mosi has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver spi_csn on net spi_csn has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(122) | tristate driver spi_sclk on net spi_sclk has its enable tied to GND (module control_soc_demo) @N:BN116 : modem.v(99) | Removing sequential instance u_modem.rin_d1 of view:PrimLib.dffs(prim) because there are no references to its outputs @N:BN116 : isp8_flow_cntl.v(351) | Removing sequential instance ie_flag of view:PrimLib.dffre(prim) because there are no references to its outputs @W:BN132 : modem.v(99) | Removing sequential instance UART_INST.u_modem.dsrn_d1, because it is equivalent to instance UART_INST.u_modem.dcdn_d1 @W:BN132 : modem.v(99) | Removing sequential instance UART_INST.u_modem.dcdn_d1, because it is equivalent to instance UART_INST.u_modem.ctsn_d1 Available hyper_sources - for debug and ip models None Found Warning: Found 2 combinational loops! @W:BN137 : control_soc_demo.v(322) | Found combinational loop during mapping at net DebounceRingOSCb[16] 1) instance work.control_soc_demo(verilog)-DebounceRingOSCb[16], output net "DebounceRingOSCb[16]" in work.control_soc_demo(verilog) @W:BN137 : ringosc.v(58) | Found combinational loop during mapping at net RingOSC_inst.RingOSCb[6] 2) instance work.clkselect_wb(verilog)-RingOSC_inst.RingOSCb[6], output net "RingOSC_inst.RingOSCb[6]" in work.clkselect_wb(verilog) End of loops @N:MT206 : | Autoconstrain Mode is ON @N:FA239 : control_soc_demo.v(911) | Rom LCD4Seg_2[6:0] mapped in logic. @N:FA239 : control_soc_demo.v(889) | Rom LCD3Seg_2[6:0] mapped in logic. @N:FA239 : control_soc_demo.v(867) | Rom LCD2Seg_2[6:0] mapped in logic. @N:FA239 : control_soc_demo.v(845) | Rom LCD1Seg_2[6:0] mapped in logic. @N:MO106 : control_soc_demo.v(911) | Found ROM, 'LCD4Seg_2[6:0]', 16 words by 7 bits @N:MO106 : control_soc_demo.v(889) | Found ROM, 'LCD3Seg_2[6:0]', 16 words by 7 bits @N:MO106 : control_soc_demo.v(867) | Found ROM, 'LCD2Seg_2[6:0]', 16 words by 7 bits @N:MO106 : control_soc_demo.v(845) | Found ROM, 'LCD1Seg_2[6:0]', 16 words by 7 bits Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB) Encoding state machine work.control_soc_demo(verilog)-state[2:0] original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: : control_soc_demo.v(688) | Found counter in view:work.control_soc_demo(verilog) inst FastCounter4[15:0] @N: : control_soc_demo.v(688) | Found counter in view:work.control_soc_demo(verilog) inst FastCounter3[15:0] @N: : control_soc_demo.v(688) | Found counter in view:work.control_soc_demo(verilog) inst FastCounter2[15:0] @N: : control_soc_demo.v(688) | Found counter in view:work.control_soc_demo(verilog) inst FastCounter1[15:0] @N: : control_soc_demo.v(723) | Found counter in view:work.control_soc_demo(verilog) inst SampleCounter[16:0] @N: : reset_gen.v(63) | Found counter in view:work.control_soc_demo(verilog) inst reset_gen_inst.reset_counter[3:0] @N: : clksource_wb.v(170) | Found counter in view:work.clkselect_wb(verilog) inst RingOSCEnbDelay[4:0] @N: : oscclkclean.v(128) | Found counter in view:work.oscclkclean(verilog) inst RingOSCcnt[9:0] @N: : oscclkclean.v(111) | Found counter in view:work.oscclkclean(verilog) inst CalRingOSCcnt[9:0] @W:BN132 : modem.v(99) | Removing instance UART_INST.u_modem.msr_reg[1], because it is equivalent to instance UART_INST.u_modem.msr_reg[0] @W:BN132 : modem.v(99) | Removing instance UART_INST.u_modem.msr_reg[3], because it is equivalent to instance UART_INST.u_modem.msr_reg[0] @W:BN132 : modem.v(99) | Removing instance UART_INST.u_modem.msr_reg[7], because it is equivalent to instance UART_INST.u_modem.msr_reg[6] @W:BN132 : modem.v(99) | Removing instance UART_INST.u_modem.msr_reg[6], because it is equivalent to instance UART_INST.u_modem.msr_reg[5] @W:BN132 : modem.v(99) | Removing instance UART_INST.u_modem.msr_reg[5], because it is equivalent to instance UART_INST.u_modem.msr_reg[4] Encoding state machine work.intface_Z7(verilog)-genblk13\.cs_state[4:0] original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[15], because it is equivalent to instance UART_INST.u_intface.divisor[14] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[14], because it is equivalent to instance UART_INST.u_intface.divisor[13] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[13], because it is equivalent to instance UART_INST.u_intface.divisor[12] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[12], because it is equivalent to instance UART_INST.u_intface.divisor[11] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[11], because it is equivalent to instance UART_INST.u_intface.divisor[10] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[9], because it is equivalent to instance UART_INST.u_intface.divisor[10] @W:BN132 : intface.v(223) | Removing instance UART_INST.u_intface.divisor[8], because it is equivalent to instance UART_INST.u_intface.divisor[10] @N:BN116 : intface.v(223) | Removing sequential instance divisor[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : intface.v(223) | Boundary register divisor[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Encoding state machine work.rxcver_8s_0s_0_1_2_3_4_XO(verilog)-cs_state[4:0] original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N: : rxcver.v(269) | Found counter in view:work.rxcver_8s_0s_0_1_2_3_4_XO(verilog) inst databit_recved_num[3:0] @N:MF179 : rxcver.v(286) | Found 16 bit by 16 bit '==' comparator, 'cs_state12' Encoding state machine work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog)-genblk2\.genblk1\.tx_state[6:0] original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : txmitt.v(275) | Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk2\.genblk1\.counter[15:0] @N: : sigmadelta_adc.v(124) | Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst sigma[9:0] @N: : sigmadelta_adc.v(172) | Found counter in view:work.sigmadelta_adc_8s_10s_3s(verilog) inst counter[9:0] Encoding state machine work.LCDEncoding4to1com_LCD_COM0enc_inst_LCD_COM0enc_inst_LCD_COM0enc_inst(verilog)-state[7:0] original code -> new code 000 -> 000 001 -> 001 010 -> 010 011 -> 011 100 -> 100 101 -> 101 110 -> 110 111 -> 111 Encoding state machine work.PWM(verilog)-state[2:0] original code -> new code 000 -> 00 001 -> 01 010 -> 10 Encoding state machine work.LCDEncoding4to1com_LCD_COM0enc_inst_LCD_COM0enc_inst(verilog)-state[7:0] original code -> new code 000 -> 000 001 -> 001 010 -> 010 011 -> 011 100 -> 100 101 -> 101 110 -> 110 111 -> 111 Encoding state machine work.LCDEncoding4to1com_LCD_COM0enc_inst(verilog)-state[7:0] original code -> new code 000 -> 000 001 -> 001 010 -> 010 011 -> 011 100 -> 100 101 -> 101 110 -> 110 111 -> 111 Encoding state machine work.LCDEncoding4to1com(verilog)-state[7:0] original code -> new code 000 -> 000 001 -> 001 010 -> 010 011 -> 011 100 -> 100 101 -> 101 110 -> 110 111 -> 111 Encoding state machine work.LCDEncoding4to1(verilog)-state[7:0] original code -> new code 000 -> 000 001 -> 001 010 -> 010 011 -> 011 100 -> 100 101 -> 101 110 -> 110 111 -> 111 @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[0], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[0] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[1], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[1] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[2], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[2] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[3], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[3] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[4], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[4] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[5], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[5] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[6], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[6] @W:BN132 : isp8_flow_cntl.v(209) | Removing instance lm8_inst.u1_isp8.u1_isp8_flow_cntl.dout_alu_reg[7], because it is equivalent to instance lm8_inst.u1_isp8.din_rd1[7] @N:BN116 : box_ave.v(108) | Removing sequential instance adc_wb_inst.adc_inst.SSD_ADC.box_ave.result_valid of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : box_ave.v(108) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.result_valid has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : modem.v(99) | Removing sequential instance UART_INST.u_modem.msr_reg[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : modem.v(99) | Boundary register UART_INST.u_modem.msr_reg[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(330) | Removing sequential instance lm8_inst.u1_isp8.genblk5\.page_ptr1[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(342) | Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(342) | Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(342) | Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : isp8_core.v(342) | Removing sequential instance lm8_inst.u1_isp8.genblk6\.page_ptr2[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 87MB) @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_3, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_1 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_2, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_1 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_1, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_0 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_0, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_2, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_1 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_3, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_1 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_1, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_0 @N:BN116 : clk_switch.v(21) | Removing sequential instance clkselect_wb_inst.clk_switch_inst1.q3_0 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : clk_switch.v(21) | Boundary register clkselect_wb_inst.clk_switch_inst1.q3_0 has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_3, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_1 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_2, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_1 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_1, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4_0 @W:BN132 : clk_switch.v(29) | Removing instance clkselect_wb_inst.clk_switch_inst1.q4_0, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q4 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_3, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_1 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_4, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_1 @W:BN132 : clk_switch.v(21) | Removing instance clkselect_wb_inst.clk_switch_inst1.q3_2, because it is equivalent to instance clkselect_wb_inst.clk_switch_inst1.q3_1 #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== clkselect_wb_inst.clk_switch_inst1.q3_1:C Not Done clkselect_wb_inst.RingOSCclk_ret:C Not Done PushButton_Debouncer_inst.Pushed:C Not Done reset_gen_inst.rst2_out:C Not Done DebounceRingOSCen:C Done USERSTDBY:C Done lcdcounter[3]:C Not Done lcdcounter[12]:C Not Done LCD4Digit_inst.LCD_12_inst.state[1]:C Done LCD4Digit_inst.LCD_12_inst.state[0]:C Done LCD4Digit_inst.LCD_12enc_inst.state[2]:C Done LCD4Digit_inst.LCD_12enc_inst.state[1]:C Done LCD4Digit_inst.LCD_12enc_inst.state[0]:C Done LCD4Digit_inst.LCD_11_inst.state[1]:C Done LCD4Digit_inst.LCD_11_inst.state[0]:C Done LCD4Digit_inst.LCD_11enc_inst.state[2]:C Done LCD4Digit_inst.LCD_11enc_inst.state[1]:C Done LCD4Digit_inst.LCD_11enc_inst.state[0]:C Done LCD4Digit_inst.LCD_10_inst.state[1]:C Done LCD4Digit_inst.LCD_10_inst.state[0]:C Done LCD4Digit_inst.LCD_10enc_inst.state[2]:C Done LCD4Digit_inst.LCD_10enc_inst.state[1]:C Done LCD4Digit_inst.LCD_10enc_inst.state[0]:C Done LCD4Digit_inst.LCD_9_inst.state[1]:C Done LCD4Digit_inst.LCD_9_inst.state[0]:C Done LCD4Digit_inst.LCD_9enc_inst.state[2]:C Done LCD4Digit_inst.LCD_9enc_inst.state[1]:C Done LCD4Digit_inst.LCD_9enc_inst.state[0]:C Done LCD4Digit_inst.LCD_8_inst.state[1]:C Done LCD4Digit_inst.LCD_8_inst.state[0]:C Done LCD4Digit_inst.LCD_8enc_inst.state[2]:C Done LCD4Digit_inst.LCD_8enc_inst.state[1]:C Done LCD4Digit_inst.LCD_8enc_inst.state[0]:C Done LCD4Digit_inst.LCD_7_inst.state[1]:C Done LCD4Digit_inst.LCD_7_inst.state[0]:C Done LCD4Digit_inst.LCD_7enc_inst.state[2]:C Done LCD4Digit_inst.LCD_7enc_inst.state[1]:C Done LCD4Digit_inst.LCD_7enc_inst.state[0]:C Done LCD4Digit_inst.LCD_6_inst.state[1]:C Done LCD4Digit_inst.LCD_6_inst.state[0]:C Done LCD4Digit_inst.LCD_6enc_inst.state[2]:C Done LCD4Digit_inst.LCD_6enc_inst.state[1]:C Done LCD4Digit_inst.LCD_6enc_inst.state[0]:C Done LCD4Digit_inst.LCD_5_inst.state[1]:C Done LCD4Digit_inst.LCD_5_inst.state[0]:C Done LCD4Digit_inst.LCD_5enc_inst.state[2]:C Done LCD4Digit_inst.LCD_5enc_inst.state[1]:C Done LCD4Digit_inst.LCD_5enc_inst.state[0]:C Done LCD4Digit_inst.LCD_COM3_inst.state[1]:C Done LCD4Digit_inst.LCD_COM3_inst.state[0]:C Done LCD4Digit_inst.LCD_COM3enc_inst.state[2]:C Done LCD4Digit_inst.LCD_COM3enc_inst.state[1]:C Done LCD4Digit_inst.LCD_COM3enc_inst.state[0]:C Done LCD4Digit_inst.LCD_COM2_inst.state[1]:C Done LCD4Digit_inst.LCD_COM2_inst.state[0]:C Done LCD4Digit_inst.LCD_COM2enc_inst.state[2]:C Done LCD4Digit_inst.LCD_COM2enc_inst.state[1]:C Done LCD4Digit_inst.LCD_COM2enc_inst.state[0]:C Done LCD4Digit_inst.LCD_COM1_inst.state[1]:C Done LCD4Digit_inst.LCD_COM1_inst.state[0]:C Done LCD4Digit_inst.LCD_COM1enc_inst.state[2]:C Done LCD4Digit_inst.LCD_COM1enc_inst.state[1]:C Done LCD4Digit_inst.LCD_COM1enc_inst.state[0]:C Done LCD4Digit_inst.LCD_COM0_inst.state[1]:C Done LCD4Digit_inst.LCD_COM0_inst.state[0]:C Done LCD4Digit_inst.LCD_COM0enc_inst.state[2]:C Done LCD4Digit_inst.LCD_COM0enc_inst.state[1]:C Done LCD4Digit_inst.LCD_COM0enc_inst.state[0]:C Done clkselect_wb_inst.RingOSCEnbDelay[4:0]:C Not Done clkselect_wb_inst.clk_switch_inst1.q2:C Not Done clkselect_wb_inst.clk_switch_inst1.q1:C Not Done clkselect_wb_inst.clk_switch_inst1.q3:C Not Done clkselect_wb_inst.oscclkclean_inst.RingOSCclk:C Not Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 88MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 88MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 88MB) Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 88MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 88MB) Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 86MB peak: 88MB) Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 95MB peak: 97MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -2.62ns 840 / 623 2 0h:00m:03s -2.62ns 828 / 623 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -2.32ns 835 / 626 2 0h:00m:05s -2.32ns 835 / 626 3 0h:00m:05s -2.32ns 835 / 626 4 0h:00m:05s -2.32ns 835 / 626 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -2.32ns 835 / 626 2 0h:00m:05s -2.32ns 835 / 626 3 0h:00m:05s -2.32ns 835 / 626 4 0h:00m:06s -2.32ns 835 / 626 ------------------------------------------------------------ @N:MF322 : | Retiming summary: 2 registers retimed to 4 ##### BEGIN RETIMING REPORT ##### Retiming summary : 2 registers retimed to 4 Original and Pipelined registers replaced by retiming : clkselect_wb_inst.oscclkclean_inst.RingOSCclk_0 clkselect_wb_inst.oscclkclean_inst.RingOSCclk_1 New registers created by retiming : clkselect_wb_inst.RingOSCclk_ret clkselect_wb_inst.RingOSCclk_ret_1 clkselect_wb_inst.RingOSCclk_ret_3 clkselect_wb_inst.RingOSCclk_ret_5 ##### END RETIMING REPORT ##### Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:06s; Memory used current: 95MB peak: 97MB) @N:FX164 : | The option to pack flops in the IOB has not been specified @W:MO111 : control_soc_demo.v(88) | tristate driver spi_sclk_obuft.un1[0] on net spi_sclk has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(89) | tristate driver spi_csn_obuft.un1[0] on net spi_csn has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(90) | tristate driver spi_mosi_obuft.un1[0] on net spi_mosi has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(92) | tristate driver spi_miso_obuft.un1[0] on net spi_miso has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(96) | tristate driver I2CAlert_obuft.un1[0] on net I2CAlert has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(97) | tristate driver scl_obuft.un1[0] on net scl has its enable tied to GND (module control_soc_demo) @W:MO111 : control_soc_demo.v(98) | tristate driver sda_obuft.un1[0] on net sda has its enable tied to GND (module control_soc_demo) @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnb1.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(91) | Boundary register clkselect_wb_inst.SelectClockwb.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(331) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.zero_flag.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.br_enb_reg.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(302) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.carry_flag_int.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(232) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.addr_jmp_reg_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_flow_cntl.v(283) | Boundary register lm8_inst.u1_isp8.u1_isp8_flow_cntl.pc_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(342) | Boundary register lm8_inst.u1_isp8.genblk6\.page_ptr2_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : isp8_core.v(330) | Boundary register lm8_inst.u1_isp8.genblk5\.page_ptr1_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(329) | Boundary register UART_INST.u_intface.genblk7\.data_8bit_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.lcr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(351) | Boundary register UART_INST.u_intface.genblk8\.thr_nonfifo_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : intface.v(223) | Boundary register UART_INST.u_intface.divisor_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(269) | Boundary register UART_INST.u_rxcver.rsr_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(410) | Boundary register UART_INST.u_rxcver.rbr_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(155) | Boundary register UART_INST.u_rxcver.hunt.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : rxcver.v(208) | Boundary register UART_INST.u_rxcver.genblk1\.genblk1\.rbr_datardy.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tsr_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tx_parity.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.tx_output.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(446) | Boundary register UART_INST.u_txmitt.genblk4\.thr_empty.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(418) | Boundary register UART_INST.u_txmitt.genblk3\.genblk1\.tsr_empty.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.accum_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(166) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.ave_data_out_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : box_ave.v(146) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.box_ave.accum_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(723) | Boundary register touched4.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(723) | Boundary register touched2.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : led_sw_wb.v(67) | Boundary register lcd_sw_inst.LCD3_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : led_sw_wb.v(67) | Boundary register lcd_sw_inst.LCD3_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : led_sw_wb.v(67) | Boundary register lcd_sw_inst.LCD3_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : led_sw_wb.v(67) | Boundary register lcd_sw_inst.LCD3_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_20_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_21_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_22_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_23_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_24_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_19_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(1032) | Boundary register NextStateDelay_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : txmitt.v(275) | Boundary register UART_INST.u_txmitt.genblk2\.genblk1\.counter_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter4_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter3_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter2_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : control_soc_demo.v(688) | Boundary register FastCounter1_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnbDelay_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnbDelay_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnbDelay_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnbDelay_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : clksource_wb.v(170) | Boundary register clkselect_wb_inst.RingOSCEnbDelay_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_0_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : sigmadelta_adc.v(124) | Boundary register adc_wb_inst.adc_inst.SSD_ADC.sigma_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. --------------------------------------- Resource Usage Report Part: lcmxo2_1200ze-3 Register bits: 626 of 1280 (49%) Latch bits: 1 PIC Latch: 0 I/O cells: 34 Details: BB: 4 CCU2D: 145 FD1P3AX: 37 FD1P3BX: 15 FD1P3DX: 281 FD1S1D: 1 FD1S3AX: 58 FD1S3BX: 13 FD1S3DX: 206 FD1S3IX: 9 FD1S3JX: 1 GSR: 1 IB: 4 IFS1P3DX: 2 ILVDS: 2 INV: 41 OBZ: 24 OFS1P3BX: 4 ORCALUT4: 794 PFUMX: 32 PUR: 1 VHI: 1 VLO: 1 @W:MT453 : | clock period is too big for clock oscclkclean|RingOSCclk_inferred_clock, changing period from 10000.0 to 1000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 5000.0 ns to 500.0 ns. @W:MT453 : | clock period is too big for clock clkselect_wb|oscclk_inferred_clock, changing period from 10000.0 to 1000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 5000.0 ns to 500.0 ns. Finished restoring hierarchy (Time elapsed 0h:00m:06s; Memory used current: 96MB peak: 97MB) Writing Analyst data base C:\Documents and Settings\cwest\Desktop\MachXO2_Pico_Demos\SoC\Demo_MachXO2_Pico_SoC10_Diamond_Working\Demo_MachXO2_Control_SoC\project\impl1\impl1.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:07s; Memory used current: 93MB peak: 97MB) Writing EDIF Netlist and constraint files E-2010.09L-SP2 Beta @N:BW106 : | Synplicity Constraint File capacitance units will use default value of 1pF Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:07s; Memory used current: 98MB peak: 100MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 97MB peak: 100MB) ================= Gated clock report ================= The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting -------------------------------------------------------------------------------------------------------------------------------------------------------- clkselect_wb_inst.RingOSCEnb1 CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found clkselect_wb_inst.RingOSCEnbDelay[4] CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found clkselect_wb_inst.RingOSCEnbDelay[3] CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found clkselect_wb_inst.RingOSCEnbDelay[2] CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found clkselect_wb_inst.RingOSCEnbDelay[1] CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found clkselect_wb_inst.RingOSCEnbDelay[0] CK clkselect_wb_inst.clk_switch_inst1.un1_clkselect_wb_inst_0 Multiple declared clocks found ======================================================================================================================================================== ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 97MB peak: 100MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 97MB peak: 100MB) @N:MF333 : | Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 97MB peak: 100MB) Warning: Found 2 combinational loops! @W:BN137 : control_soc_demo.v(322) | Found combinational loop during mapping at net DebounceRingOSCb[16] 1) instance work.control_soc_demo(verilog)-DebounceRingOSCb[16], output net "DebounceRingOSCb[16]" in work.control_soc_demo(verilog) @W:BN137 : ringosc.v(58) | Found combinational loop during mapping at net RingOSCb[6] 2) instance work.RingOSC(netlist)-RingOSCb[6], output net "RingOSCb[6]" in work.RingOSC(netlist) End of loops @W:MT246 : powercntr.v(25) | Blackbox PCNTR is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : efb_module.v(83) | Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : rom_ebr_wb.v(68) | Blackbox pmi_rom_1024s_10s_8s_noreg_disable_sync_menu\.hex_hex_XO2_pmi_rom_Z8 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : lm8_top.v(130) | Blackbox pmi_distributed_spram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_spram_Z5 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : isp8_core.v(434) | Blackbox pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_XO2_pmi_distributed_dpram_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : isp8_core.v(320) | Blackbox pmi_rom_2048s_11s_18s_noreg_disable_async_prom_init\.hex_hex_XO2_pmi_rom_Z2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : isp8_flow_cntl.v(394) | Blackbox pmi_distributed_spram_16s_4s_13s_noreg_none_binary_XO2_pmi_distributed_spram_Z1 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : isp8_alu.v(95) | Blackbox pmi_addsub_8s_8s_off_XO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : clksource_wb.v(125) | Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock control_soc_demo|clk_USB with period 1000.00ns. A user-defined clock should be declared on object "p:clk_USB" @W:MT420 : | Found inferred clock PushButton_Debouncer|Pushed_inferred_clock with period 1.00ns. A user-defined clock should be declared on object "n:PushButton_Debouncer_inst.Pushed" @W:MT420 : | Found inferred clock oscclkclean|RingOSCclk_inferred_clock with period 6.92ns. A user-defined clock should be declared on object "n:clkselect_wb_inst.oscclkclean_inst.RingOSCclk" @W:MT420 : | Found inferred clock clkselect_wb|oscclk_inferred_clock with period 6.92ns. A user-defined clock should be declared on object "n:clkselect_wb_inst.oscclk" ##### START OF TIMING REPORT #####[ # Timing Report written on Sat Feb 19 18:34:11 2011 # Top view: control_soc_demo Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -2.255 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------- PushButton_Debouncer|Pushed_inferred_clock 1000.0 MHz 307.2 MHz 1.000 3.255 -2.255 inferred Autoconstr_clkgroup_0 clkselect_wb|oscclk_inferred_clock 144.5 MHz 122.8 MHz 6.919 8.140 -1.221 inferred Autoconstr_clkgroup_5 control_soc_demo|clk_USB 1.0 MHz NA 1000.000 NA NA inferred Autoconstr_clkgroup_1 oscclkclean|RingOSCclk_inferred_clock 144.5 MHz 122.8 MHz 6.919 8.140 -1.221 inferred Autoconstr_clkgroup_4 System 181.5 MHz 154.3 MHz 5.509 6.481 -0.972 system system_clkgroup ===================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 5.509 -0.972 | No paths - | No paths - | No paths - System oscclkclean|RingOSCclk_inferred_clock | 6.919 1.083 | No paths - | No paths - | No paths - System clkselect_wb|oscclk_inferred_clock | 6.919 1.083 | No paths - | No paths - | No paths - PushButton_Debouncer|Pushed_inferred_clock System | No paths - | No paths - | No paths - | 1.000 -2.255 control_soc_demo|clk_USB oscclkclean|RingOSCclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - control_soc_demo|clk_USB clkselect_wb|oscclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - oscclkclean|RingOSCclk_inferred_clock System | 6.919 0.061 | No paths - | No paths - | No paths - oscclkclean|RingOSCclk_inferred_clock oscclkclean|RingOSCclk_inferred_clock | 6.919 -1.221 | No paths - | No paths - | No paths - oscclkclean|RingOSCclk_inferred_clock clkselect_wb|oscclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - clkselect_wb|oscclk_inferred_clock System | 6.919 0.061 | No paths - | No paths - | No paths - clkselect_wb|oscclk_inferred_clock oscclkclean|RingOSCclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - clkselect_wb|oscclk_inferred_clock clkselect_wb|oscclk_inferred_clock | 6.919 -1.221 | No paths - | No paths - | No paths - =========================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PushButton_Debouncer|Pushed_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------- DebounceRingOSCen.res_lat PushButton_Debouncer|Pushed_inferred_clock FD1S1D Q DebounceRingOSCen.o3 1.044 -2.255 =========================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.894 - Propagation time: 3.149 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.255 Number of logic level(s): 2 Starting point: DebounceRingOSCen.res_lat / Q Ending point: DebounceRingOSCen.res_reg / D The start point is clocked by PushButton_Debouncer|Pushed_inferred_clock [falling] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ DebounceRingOSCen.res_lat FD1S1D Q Out 1.044 1.044 - DebounceRingOSCen.o3 Net - - - - 2 DebounceRingOSCen.res_reg_0_RNIGGEU ORCALUT4 C In 0.000 1.044 - DebounceRingOSCen.res_reg_0_RNIGGEU ORCALUT4 Z Out 1.017 2.061 - DebounceRingOSCen Net - - - - 1 DebounceRingOSCene ORCALUT4 B In 0.000 2.061 - DebounceRingOSCene ORCALUT4 Z Out 1.089 3.149 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg FD1S3DX D In 0.000 3.149 - ====================================================================================================== Path information for path number 2: Requested Period: 1.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.894 - Propagation time: 3.149 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.255 Number of logic level(s): 2 Starting point: DebounceRingOSCen.res_lat / Q Ending point: DebounceRingOSCen.res_reg_0 / D The start point is clocked by PushButton_Debouncer|Pushed_inferred_clock [falling] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ DebounceRingOSCen.res_lat FD1S1D Q Out 1.044 1.044 - DebounceRingOSCen.o3 Net - - - - 2 DebounceRingOSCen.res_reg_0_RNIGGEU ORCALUT4 C In 0.000 1.044 - DebounceRingOSCen.res_reg_0_RNIGGEU ORCALUT4 Z Out 1.017 2.061 - DebounceRingOSCen Net - - - - 1 DebounceRingOSCene ORCALUT4 B In 0.000 2.061 - DebounceRingOSCene ORCALUT4 Z Out 1.089 3.149 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg_0 FD1S3BX D In 0.000 3.149 - ====================================================================================================== ==================================== Detailed Report for Clock: clkselect_wb|oscclk_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- NextStateDelay[0] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[0] 1.180 -1.221 NextStateDelay[1] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[1] 1.108 -1.149 NextStateDelay[2] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[2] 1.108 -1.149 NextStateDelay[3] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[3] 1.108 -1.149 NextStateDelay[4] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[4] 1.108 -1.006 NextStateDelay[5] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[5] 1.108 -1.006 NextStateDelay[6] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[6] 1.108 -1.006 NextStateDelay[7] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[7] 1.108 -1.006 NextStateDelay[8] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[8] 1.044 -0.942 NextStateDelay[9] clkselect_wb|oscclk_inferred_clock FD1P3DX Q NextStateDelay[9] 1.044 -0.942 ========================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------- NextStateDelay[0] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[0] 7.176 -1.221 NextStateDelay[1] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[1] 7.176 -1.221 NextStateDelay[2] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[2] 7.176 -1.221 NextStateDelay[3] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[3] 7.176 -1.221 NextStateDelay[4] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[4] 7.176 -1.221 NextStateDelay[5] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[5] 7.176 -1.221 NextStateDelay[6] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[6] 7.176 -1.221 NextStateDelay[7] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[7] 7.176 -1.221 NextStateDelay[8] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[8] 7.176 -1.221 NextStateDelay[9] clkselect_wb|oscclk_inferred_clock FD1P3DX D NextStateDelay_4[9] 7.176 -1.221 ============================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK The end point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 B In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 2: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK The end point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0_cp ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0_cp ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0_cp Net - - - - 1 un7_NextStateDelay_axb_0_par_cp_0 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_cp_0 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_cp_0_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_cp_0 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_cp_0 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_axb_4_par_cp_0_COUT Net - - - - 1 un7_NextStateDelay_axb_12_par_1 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_axb_12_par_1 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_axb_12_par_1_COUT Net - - - - 1 un7_NextStateDelay_cry_19_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_19_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_20 Net - - - - 1 un7_NextStateDelay_cry_21_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_21_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_22 Net - - - - 1 un7_NextStateDelay_cry_23_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_23_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_23_0_S1 Net - - - - 2 NextStateDelay16_21_1_0 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1_0 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1_0 Net - - - - 1 NextStateDelay16_21 ORCALUT4 D In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 B In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ========================================================================================================= Path information for path number 3: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK The end point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S0 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S0 Net - - - - 2 NextStateDelay16_22_10 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_22_10 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_22_10 Net - - - - 1 NextStateDelay16_22 ORCALUT4 D In 0.000 6.430 - NextStateDelay16_22 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_22 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 C In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 4: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: state[0] / D The start point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK The end point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 state_ns_1_0_.g0_0 ORCALUT4 A In 0.000 7.780 - state_ns_1_0_.g0_0 ORCALUT4 Z Out 0.617 8.397 - state_ns[0] Net - - - - 1 state[0] FD1S3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 5: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: state[1] / D The start point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK The end point is clocked by clkselect_wb|oscclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 state_ns_1_0_.g0 ORCALUT4 A In 0.000 7.780 - state_ns_1_0_.g0 ORCALUT4 Z Out 0.617 8.397 - state_ns_1_0_.m7_N_4 Net - - - - 1 state[1] FD1S3DX D In 0.000 8.397 - ====================================================================================================== ==================================== Detailed Report for Clock: oscclkclean|RingOSCclk_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------- NextStateDelay[0] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[0] 1.180 -1.221 NextStateDelay[1] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[1] 1.108 -1.149 NextStateDelay[2] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[2] 1.108 -1.149 NextStateDelay[3] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[3] 1.108 -1.149 NextStateDelay[4] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[4] 1.108 -1.006 NextStateDelay[5] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[5] 1.108 -1.006 NextStateDelay[6] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[6] 1.108 -1.006 NextStateDelay[7] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[7] 1.108 -1.006 NextStateDelay[8] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[8] 1.044 -0.942 NextStateDelay[9] oscclkclean|RingOSCclk_inferred_clock FD1P3DX Q NextStateDelay[9] 1.044 -0.942 ============================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- NextStateDelay[0] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[0] 7.176 -1.221 NextStateDelay[1] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[1] 7.176 -1.221 NextStateDelay[2] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[2] 7.176 -1.221 NextStateDelay[3] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[3] 7.176 -1.221 NextStateDelay[4] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[4] 7.176 -1.221 NextStateDelay[5] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[5] 7.176 -1.221 NextStateDelay[6] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[6] 7.176 -1.221 NextStateDelay[7] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[7] 7.176 -1.221 NextStateDelay[8] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[8] 7.176 -1.221 NextStateDelay[9] oscclkclean|RingOSCclk_inferred_clock FD1P3DX D NextStateDelay_4[9] 7.176 -1.221 =============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK The end point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 B In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 2: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK The end point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0_cp ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0_cp ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0_cp Net - - - - 1 un7_NextStateDelay_axb_0_par_cp_0 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_cp_0 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_cp_0_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_cp_0 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_cp_0 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_axb_4_par_cp_0_COUT Net - - - - 1 un7_NextStateDelay_axb_12_par_1 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_axb_12_par_1 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_axb_12_par_1_COUT Net - - - - 1 un7_NextStateDelay_cry_19_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_19_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_20 Net - - - - 1 un7_NextStateDelay_cry_21_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_21_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_22 Net - - - - 1 un7_NextStateDelay_cry_23_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_23_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_23_0_S1 Net - - - - 2 NextStateDelay16_21_1_0 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1_0 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1_0 Net - - - - 1 NextStateDelay16_21 ORCALUT4 D In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 B In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ========================================================================================================= Path information for path number 3: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: NextStateDelay[5] / D The start point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK The end point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S0 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S0 Net - - - - 2 NextStateDelay16_22_10 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_22_10 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_22_10 Net - - - - 1 NextStateDelay16_22 ORCALUT4 D In 0.000 6.430 - NextStateDelay16_22 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_22 Net - - - - 27 NextStateDelay_4[5] ORCALUT4 C In 0.000 7.780 - NextStateDelay_4[5] ORCALUT4 Z Out 0.617 8.397 - NextStateDelay_4[5] Net - - - - 1 NextStateDelay[5] FD1P3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 4: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: state[0] / D The start point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK The end point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 state_ns_1_0_.g0_0 ORCALUT4 A In 0.000 7.780 - state_ns_1_0_.g0_0 ORCALUT4 Z Out 0.617 8.397 - state_ns[0] Net - - - - 1 state[0] FD1S3DX D In 0.000 8.397 - ====================================================================================================== Path information for path number 5: Requested Period: 6.919 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.176 - Propagation time: 8.397 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.221 Number of logic level(s): 10 Starting point: NextStateDelay[0] / Q Ending point: state[1] / D The start point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK The end point is clocked by oscclkclean|RingOSCclk_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ NextStateDelay[0] FD1P3DX Q Out 1.180 1.180 - NextStateDelay[0] Net - - - - 5 un7_NextStateDelay_axb_0_par_0 ORCALUT4 A In 0.000 1.180 - un7_NextStateDelay_axb_0_par_0 ORCALUT4 Z Out 1.017 2.197 - un7_NextStateDelay_axb_0_par_0 Net - - - - 1 un7_NextStateDelay_axb_0_par_1 CCU2D A1 In 0.000 2.197 - un7_NextStateDelay_axb_0_par_1 CCU2D COUT Out 1.509 3.705 - un7_NextStateDelay_axb_0_par_1_COUT Net - - - - 1 un7_NextStateDelay_axb_4_par_1 CCU2D CIN In 0.000 3.705 - un7_NextStateDelay_axb_4_par_1 CCU2D COUT Out 0.143 3.848 - un7_NextStateDelay_cry_8 Net - - - - 1 un7_NextStateDelay_cry_9_0 CCU2D CIN In 0.000 3.848 - un7_NextStateDelay_cry_9_0 CCU2D COUT Out 0.143 3.991 - un7_NextStateDelay_cry_10 Net - - - - 1 un7_NextStateDelay_cry_11_0 CCU2D CIN In 0.000 3.991 - un7_NextStateDelay_cry_11_0 CCU2D COUT Out 0.143 4.134 - un7_NextStateDelay_cry_12 Net - - - - 1 un7_NextStateDelay_cry_13_0 CCU2D CIN In 0.000 4.134 - un7_NextStateDelay_cry_13_0 CCU2D COUT Out 0.143 4.277 - un7_NextStateDelay_cry_14 Net - - - - 1 un7_NextStateDelay_cry_15_0 CCU2D CIN In 0.000 4.277 - un7_NextStateDelay_cry_15_0 CCU2D S1 Out 1.137 5.413 - un7_NextStateDelay_cry_15_0_S1 Net - - - - 2 NextStateDelay16_21_1 ORCALUT4 C In 0.000 5.413 - NextStateDelay16_21_1 ORCALUT4 Z Out 1.017 6.430 - NextStateDelay16_21_1 Net - - - - 1 NextStateDelay16_21 ORCALUT4 C In 0.000 6.430 - NextStateDelay16_21 ORCALUT4 Z Out 1.350 7.780 - NextStateDelay16_21 Net - - - - 27 state_ns_1_0_.g0 ORCALUT4 A In 0.000 7.780 - state_ns_1_0_.g0 ORCALUT4 Z Out 0.617 8.397 - state_ns_1_0_.m7_N_4 Net - - - - 1 state[1] FD1S3DX D In 0.000 8.397 - ====================================================================================================== ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ PushButton_Debouncer_inst.SampleReg[5] System FD1S3DX Q SampleReg[5] 1.148 -0.972 PushButton_Debouncer_inst.SampleReg[13] System FD1S3DX Q SampleReg[13] 1.148 -0.027 PushButton_Debouncer_inst.SampleReg[14] System FD1S3DX Q SampleReg[14] 1.148 -0.027 PushButton_Debouncer_inst.SampleReg[15] System FD1S3DX Q SampleReg[15] 1.148 -0.027 PushButton_Debouncer_inst.SampleReg[16] System FD1S3DX Q SampleReg[16] 1.148 -0.027 PushButton_Debouncer_inst.SampleReg[29] System FD1S3DX Q SampleReg[29] 1.148 -0.027 PushButton_Debouncer_inst.SampleReg[1] System FD1S3DX Q SampleReg[1] 1.108 0.013 PushButton_Debouncer_inst.SampleReg[2] System FD1S3DX Q SampleReg[2] 1.108 0.013 PushButton_Debouncer_inst.SampleReg[3] System FD1S3DX Q SampleReg[3] 1.108 0.013 PushButton_Debouncer_inst.SampleReg[4] System FD1S3DX Q SampleReg[4] 1.108 0.013 ================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ clkselect_wb_inst.oscclkclean_inst.RingOSCclk System FD1S3DX D RingOSCclke_0 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[0] System FD1P3DX D RingOSCcnt_lm[0] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[1] System FD1P3DX D RingOSCcnt_lm[1] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[2] System FD1P3DX D RingOSCcnt_lm[2] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[3] System FD1P3DX D RingOSCcnt_lm[3] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[4] System FD1P3DX D RingOSCcnt_lm[4] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[5] System FD1P3DX D RingOSCcnt_lm[5] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[6] System FD1P3DX D RingOSCcnt_lm[6] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[7] System FD1P3DX D RingOSCcnt_lm[7] 5.766 0.689 clkselect_wb_inst.oscclkclean_inst.RingOSCcnt[8] System FD1P3DX D RingOSCcnt_lm[8] 5.766 0.689 ============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.509 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.404 - Propagation time: 6.376 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.972 Number of logic level(s): 5 Starting point: PushButton_Debouncer_inst.SampleReg[5] / Q Ending point: DebounceRingOSCen.res_reg / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ PushButton_Debouncer_inst.SampleReg[5] FD1S3DX Q Out 1.148 1.148 - SampleReg[5] Net - - - - 4 PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 B In 0.000 1.148 - PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 Z Out 1.017 2.165 - g0_i_o4_0 Net - - - - 1 PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 D In 0.000 2.165 - PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 Z Out 1.017 3.181 - g0_i_m2_1_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 D In 0.000 3.181 - PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 Z Out 1.017 4.198 - g0_i_m2_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 D In 0.000 4.198 - PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 Z Out 1.089 5.287 - N_15 Net - - - - 2 DebounceRingOSCene ORCALUT4 C In 0.000 5.287 - DebounceRingOSCene ORCALUT4 Z Out 1.089 6.376 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg FD1S3DX D In 0.000 6.376 - ================================================================================================================== Path information for path number 2: Requested Period: 5.509 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.404 - Propagation time: 6.376 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.972 Number of logic level(s): 5 Starting point: PushButton_Debouncer_inst.SampleReg[5] / Q Ending point: DebounceRingOSCen.res_reg_0 / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ PushButton_Debouncer_inst.SampleReg[5] FD1S3DX Q Out 1.148 1.148 - SampleReg[5] Net - - - - 4 PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 B In 0.000 1.148 - PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 Z Out 1.017 2.165 - g0_i_o4_0 Net - - - - 1 PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 D In 0.000 2.165 - PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 Z Out 1.017 3.181 - g0_i_m2_1_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 D In 0.000 3.181 - PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 Z Out 1.017 4.198 - g0_i_m2_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 D In 0.000 4.198 - PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 Z Out 1.089 5.287 - N_15 Net - - - - 2 DebounceRingOSCene ORCALUT4 C In 0.000 5.287 - DebounceRingOSCene ORCALUT4 Z Out 1.089 6.376 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg_0 FD1S3BX D In 0.000 6.376 - ================================================================================================================== Path information for path number 3: Requested Period: 5.509 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.766 - Propagation time: 5.904 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.138 Number of logic level(s): 5 Starting point: PushButton_Debouncer_inst.SampleReg[5] / Q Ending point: USERSTDBY / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ PushButton_Debouncer_inst.SampleReg[5] FD1S3DX Q Out 1.148 1.148 - SampleReg[5] Net - - - - 4 PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 B In 0.000 1.148 - PushButton_Debouncer_inst.SampleReg_RNI69IQ[5] ORCALUT4 Z Out 1.017 2.165 - g0_i_o4_0 Net - - - - 1 PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 D In 0.000 2.165 - PushButton_Debouncer_inst.SampleReg_RNIJ9R62[6] ORCALUT4 Z Out 1.017 3.181 - g0_i_m2_1_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 D In 0.000 3.181 - PushButton_Debouncer_inst.Pushed9_4_RNIBBU73 ORCALUT4 Z Out 1.017 4.198 - g0_i_m2_1 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 D In 0.000 4.198 - PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 Z Out 1.089 5.287 - N_15 Net - - - - 2 USERSTDBYe ORCALUT4 B In 0.000 5.287 - USERSTDBYe ORCALUT4 Z Out 0.617 5.904 - USERSTDBYe_0 Net - - - - 1 USERSTDBY FD1S3DX D In 0.000 5.904 - ================================================================================================================== Path information for path number 4: Requested Period: 5.509 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.404 - Propagation time: 5.431 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.027 Number of logic level(s): 4 Starting point: PushButton_Debouncer_inst.SampleReg[13] / Q Ending point: DebounceRingOSCen.res_reg / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------- PushButton_Debouncer_inst.SampleReg[13] FD1S3DX Q Out 1.148 1.148 - SampleReg[13] Net - - - - 4 PushButton_Debouncer_inst.Pushed9_19 ORCALUT4 A In 0.000 1.148 - PushButton_Debouncer_inst.Pushed9_19 ORCALUT4 Z Out 1.017 2.165 - Pushed9_19 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_28 ORCALUT4 A In 0.000 2.165 - PushButton_Debouncer_inst.Pushed9_28 ORCALUT4 Z Out 1.089 3.253 - Pushed9_28 Net - - - - 2 PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 A In 0.000 3.253 - PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 Z Out 1.089 4.342 - N_15 Net - - - - 2 DebounceRingOSCene ORCALUT4 C In 0.000 4.342 - DebounceRingOSCene ORCALUT4 Z Out 1.089 5.431 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg FD1S3DX D In 0.000 5.431 - ================================================================================================================ Path information for path number 5: Requested Period: 5.509 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 5.404 - Propagation time: 5.431 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.027 Number of logic level(s): 4 Starting point: PushButton_Debouncer_inst.SampleReg[14] / Q Ending point: DebounceRingOSCen.res_reg / D The start point is clocked by System [rising] on pin CK The end point is clocked by System [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------- PushButton_Debouncer_inst.SampleReg[14] FD1S3DX Q Out 1.148 1.148 - SampleReg[14] Net - - - - 4 PushButton_Debouncer_inst.Pushed9_19 ORCALUT4 B In 0.000 1.148 - PushButton_Debouncer_inst.Pushed9_19 ORCALUT4 Z Out 1.017 2.165 - Pushed9_19 Net - - - - 1 PushButton_Debouncer_inst.Pushed9_28 ORCALUT4 A In 0.000 2.165 - PushButton_Debouncer_inst.Pushed9_28 ORCALUT4 Z Out 1.089 3.253 - Pushed9_28 Net - - - - 2 PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 A In 0.000 3.253 - PushButton_Debouncer_inst.Pushed9_28_RNIBBJG4 ORCALUT4 Z Out 1.089 4.342 - N_15 Net - - - - 2 DebounceRingOSCene ORCALUT4 C In 0.000 4.342 - DebounceRingOSCene ORCALUT4 Z Out 1.089 5.431 - DebounceRingOSCene_0 Net - - - - 2 DebounceRingOSCen.res_reg FD1S3DX D In 0.000 5.431 - ================================================================================================================ ##### END OF TIMING REPORT #####] Mapper successful! Process took 0h:00m:09s realtime, 0h:00m:08s cputime # Sat Feb 19 18:34:11 2011 ###########################################################]