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    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1

    # Written on Sat Nov 15 12:11:39 2025

    ##### DESIGN INFO #######################################################

    Top View:                "byteCounter"
    Constraint File(s):      "C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl"
                             "C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\impl_1\byteCounter_impl_1_cpe.ldc"

    ##### SUMMARY ############################################################

    Found 0 issues in 0 out of 1 constraints

    ##### DETAILS ############################################################

    Clock Relationships
    *******************

    Starting                             Ending                               |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    byteCounter|clk_p_inferred_clock     byteCounter|clk_p_inferred_clock     |     18.797           |     No paths         |     No paths         |     No paths
    =====================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Unconstrained Start/End Points
    ******************************

    p:led[0]
    p:led[1]
    p:led[2]
    p:led[3]
    p:led[4]
    p:led[5]
    p:led[6]
    p:led[7]
    p:rstn

    Inapplicable constraints
    ************************

    (none)

    Applicable constraints with issues
    **********************************

    (none)

    Constraints with matching wildcard expressions
    **********************************************

    (none)

    Library Report
    **************

    # End of Constraint Checker Report

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