                             Lattice Mapping Report File

    Design:  byteCounter
    Family:  LFMXO4
    Device:  LFMXO4-110HC
    Package: BBG484
    Performance Grade:  5

    Mapper:    version Radiant Software (64-bit) 2025.1.b.49.0
    Mapped on: Sat Nov 15 12:15:04 2025

    Design Information

    Command line:   map -pdc C:/Workarea/Projects/LFMXO4-110-EVN/Test_Code/TestCount
         er_xo4_TestLED/byteCounter/pins.pdc -i byteCounter_impl_1_syn.udb -o
         byteCounter_impl_1_map.udb -mp byteCounter_impl_1.mrp -hierrpt -inferGSR
         -gui -msgset C:/Workarea/Projects/LFMXO4-110-EVN/Test_Code/TestCounter_xo4_
         TestLED/byteCounter/promote.xml

    Design Summary

       Number of registers:          58 out of 10546 (1%)
          Number of SLICE         registers:   58 out of  9400 (1%)
          Number of PIO Input     registers:    0 out of   382 (0%)
          Number of PIO Output    registers:    0 out of   382 (0%)
          Number of PIO Tri-State registers:    0 out of   382 (0%)
       Number of LUT4s:              81 out of 9400 (1%)
          Number used as logic LUT4s:          21
          Number used as distributed RAM:       0 (6 per 16X4 RAM)
          Number used as ripple logic:         60 (2 per CCU2)
       Number of PIO sites used/reserved:     14 out of 382 (4%)
          Number of PIO sites used:       9
          Number of PIO sites reserved:   5 (per sysConfig constraint and default)
       Number of IDDR/ODDR/TDDR functions used:    0 out of   860 (0%)
       Number of IOs using at least one DDR function: 0 (0 differential)
       Number of Block RAMs:          0 out of 48 (0%)
       Number of PLLs:                0 out of 2 (0%)
       Number of DQSDLLs:             0 out of 2 (0%)
       Number of DLLDELs:             0 out of 8 (0%)
       Number of DCC:                 0 out of 400 (0%)
       Number of DCMs:                0 out of 2 (0%)
       Number of CLKDIVs:             0 out of 4 (0%)
       Number of ECLKSYNCs:           0 out of 4 (0%)
       Number of ECLKBRIDGECSs:       0 out of 2 (0%)
       Number of EFB:                 0 out of 1 (0%)
       Number of Oscillator:          1 out of 1 (100%)
       Number of GSR:                 0 out of 1 (0%)
       Number of TSALL:               0 out of 1 (0%)
       Number of JTAG:                0 out of 1 (0%)
       Number of SED:                 0 out of 1 (0%)
       Number of STARTUP:             0 out of 1 (0%)
       Number of Power Controller:    0 out of 1 (0%)
       Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)
       Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
       Number of Clocks:  1
          Net clk_p: 58 loads, 58 rising, 0 falling (Driver: Pin OSCInst0/OSC)
       Number of Clock Enables:  1
          Net trigger1: 28 loads, 28 SLICEs
       Number of LSRs:  3
          Pin rstn: 56 loads, 56 SLICEs (Net: rstn_c)
          Net trigger2.fb: 1 loads, 1 SLICEs
          Net trigger1.fb: 1 loads, 1 SLICEs
       Top 10 highest fanout non-clock nets:
          Net rstn_c: 56 loads
          Net trigger1: 29 loads
          Net led_c[0]: 3 loads
          Net led_c[1]: 3 loads
          Net led_c[2]: 3 loads
          Net led_c[3]: 3 loads
          Net led_c[4]: 3 loads
          Net led_c[5]: 3 loads
          Net led_c[6]: 3 loads
          Net led_c[7]: 3 loads

       Number of warnings:  1
       Number of criticals: 0
       Number of errors:    0

    Design Errors/Criticals/Warnings

    WARNING <51001030> - map: Using local reset signal 'rstn_c' to infer global GSR
         net.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+-------+-------+-----------+
    | IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
    |                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rstn                | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[7]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[6]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[5]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[4]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[3]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[2]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[1]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | led[0]              | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    Removed logic

    Block GSR_INST undriven or does not drive anything - clipped.
    Block rstn_pad_RNIR42Q4 was optimized away.
    Block GND_cZ was optimized away.

    ASIC Components

    Instance Name: OSCInst0
             Type: OSC

    Constraint Summary

       Total number of constraints: 10
       Total number of constraints dropped: 0

    Run Time and Memory Usage

       Total CPU Time: 4 secs
       Total REAL Time: 5 secs
       Peak Memory Usage: 117 MB
    Checksum -- map: 8acbc51a254cac313dac8c6eb216999cb404eb39
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995
         AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent
         Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems
         All rights reserved.
    Copyright (c) 2002-2025 Lattice Semiconductor
         Corporation,  All rights reserved.