`

    #Build: Synplify Pro (R) V-2023.09LR-3, Build 429R, Dec 18 2024
    #install: C:\lscc\radiant\2025.1\synpbase
    #OS: Windows 10 or later
    #Hostname: LPQPF559ZR1

    # Sat Nov 15 12:11:13 2025

    #Implementation: impl_1

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys HDL Compiler, Version comp202309synp1, Build 429R, Built Dec 18 2024 06:16:03, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys VHDL Compiler, Version comp202309synp1, Build 429R, Built Dec 18 2024 06:16:03, @

    @N: :  | Running in 64-bit mode
    Location map warning "C:\lscc\radiant\2025.1\synpbase\lib\vhd\location.map":41 - Attempted redefinition of package lfd2nx1.components
    Location map warning "C:\lscc\radiant\2025.1\synpbase\lib\vhd\location.map":45 - Attempted redefinition of package lfd2nx2.components
    Location map warning "C:\lscc\radiant\2025.1\synpbase\lib\vhd\location.map":51 - Attempted redefinition of package lfmxo5t1.components
    @N: :  | Can't find top module!
    Top entity isn't set yet!
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.vhd'.
    VHDL syntax check successful!
    File C:\lscc\radiant\2025.2p.6\synpbase\bin64\c_vhdl.exe changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\location.map changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\std.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\snps_haps_pkg.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\std1164.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\numeric.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\umr_capim.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\arith.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\synpbase\lib\vhd\unsigned.vhd changed - recompiling
    File C:\lscc\radiant\2025.2p.6\ip\pmi\pmi_lfmxo4.vhd changed - recompiling

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

    Process completed successfully.
    # Sat Nov 15 12:11:18 2025

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys Verilog Compiler, Version comp202309synp1, Build 429R, Built Dec 18 2024 06:16:03, @

    @N: :  | Running in 64-bit mode
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\lucent\lfmxo4.v" (library work)
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v" (library work)
    @N:CG334 : lscc_lfmxo4_ram_dp.v(730) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dp.v(734) | Read directive translate_on.
    @N:CG334 : lscc_lfmxo4_ram_dp.v(767) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dp.v(771) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(193) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(202) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v" (library work)
    @N:CG334 : lscc_lfmxo4_ram_dq.v(1402) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dq.v(1408) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(91) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(99) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter.v" (library work)
    @I::"C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\MyPLL\rtl\MyPLL.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 107MB)

    Process completed successfully.
    # Sat Nov 15 12:11:21 2025

    ###########################################################]
    ###########################################################[
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\lucent\lfmxo4.v" (library work)
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2025.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v" (library work)
    @N:CG334 : lscc_lfmxo4_ram_dp.v(730) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dp.v(734) | Read directive translate_on.
    @N:CG334 : lscc_lfmxo4_ram_dp.v(767) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dp.v(771) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(193) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(202) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v" (library work)
    @N:CG334 : lscc_lfmxo4_ram_dq.v(1402) | Read directive translate_off.
    @N:CG333 : lscc_lfmxo4_ram_dq.v(1408) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(91) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(99) | Read directive translate_on.
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lfmxo4.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter.v" (library work)
    @I::"C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\MyPLL\rtl\MyPLL.v" (library work)
    Verilog syntax check successful!
    Options changed - recompiling
    @N:CG364 : lfmxo4.v(1310) | Synthesizing module OSCH in library work.
    Running optimization stage 1 on OSCH .......
    Finished optimization stage 1 on OSCH (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB)
    @N:CG364 : byteCounter.v(24) | Synthesizing module byteCounter in library work.
    @N:CG179 : byteCounter.v(73) | Removing redundant assignment.
    @N:CG179 : byteCounter.v(101) | Removing redundant assignment.
    @W:CG781 : byteCounter.v(44) | Input STDBY on instance OSCInst0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration.
    @W:CG133 : byteCounter.v(35) | Object pllcntr is declared but not assigned. Either assign a value or remove the declaration.
    @W:CG360 : byteCounter.v(37) | Removing wire clk100m, as there is no assignment to it.
    @W:CG360 : byteCounter.v(38) | Removing wire pll_lock, as there is no assignment to it.
    Running optimization stage 1 on byteCounter .......
    Finished optimization stage 1 on byteCounter (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 110MB)
    Running optimization stage 2 on byteCounter .......
    Finished optimization stage 2 on byteCounter (CPU Time 0h:00m:00s, Memory Used current: 115MB peak: 115MB)
    Running optimization stage 2 on OSCH .......
    Finished optimization stage 2 on OSCH (CPU Time 0h:00m:00s, Memory Used current: 115MB peak: 115MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    Linked File:  layer0.duruntime

    At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 115MB peak: 115MB)

    Process completed successfully.
    # Sat Nov 15 12:11:24 2025

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 429R, Built Dec 18 2024 06:16:03, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Nov 15 12:11:27 2025

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  byteCounter_impl_1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB)

    Process took 0h:00m:12s realtime, 0h:00m:05s cputime

    Process completed successfully.
    # Sat Nov 15 12:11:27 2025

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 429R, Built Dec 18 2024 06:16:03, @

    @N: :  | Running in 64-bit mode
    File C:\lscc\radiant\2025.2p.6\synpbase\bin64\syn_nfilter.exe changed - recompiling
    File C:\Users\clooi\Downloads\2025.2Task\DNG-26287_XO4\XO4Board\TestCounter_xo4_TestLED\byteCounter\impl_1\synwork\byteCounter_impl_1_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 92MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Sat Nov 15 12:11:29 2025

    ###########################################################]

`
`

    Premap Report

`
`

    # Sat Nov 15 12:11:35 2025

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys Lattice Technology Pre-mapping, Version map202309lat, Build 306R, Built Mar  3 2025 21:43:36, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 199MB)

    Reading constraint file: C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl
    Reading constraint file: C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\impl_1\byteCounter_impl_1_cpe.ldc
    Linked File:  byteCounter_impl_1_scck.rpt
    See clock summary report "C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\impl_1\byteCounter_impl_1_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 199MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 199MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 204MB peak: 204MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 205MB peak: 206MB)

    NConnInternalConnection caching is on

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 255MB peak: 256MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 255MB peak: 256MB)

    Started DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 255MB peak: 256MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 255MB peak: 256MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 257MB peak: 257MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 257MB peak: 257MB)

    @N:FX1184 :  | Applying syn_allowed_resources blockrams=442 on top level netlist byteCounter

    Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 257MB peak: 258MB)

    Clock Summary
    ******************

              Start                                Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                Frequency     Period        Type         Group                     Load
    -----------------------------------------------------------------------------------------------------------------------
    0 -       byteCounter|clk_p_inferred_clock     53.2 MHz      18.797        inferred     Inferred_clkgroup_0_1     58
    =======================================================================================================================

    Clock Load Summary
    ***********************

                                         Clock     Source                 Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                                Load      Pin                    Seq Example     Seq Example       Comb Example
    ---------------------------------------------------------------------------------------------------------------------
    byteCounter|clk_p_inferred_clock     58        OSCInst0.OSC(OSCH)     trigger1.C      -                 -
    =====================================================================================================================

    @W:MT530 : bytecounter.v(94) | Found inferred clock byteCounter|clk_p_inferred_clock which controls 58 sequential elements including cnt2bits[27:0]. This clock has no specified timing constraint which may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 58 clock pin(s) of sequential element(s)
    0 instances converted, 58 sequential instances remain driven by gated/generated clocks

    ======================================================= Gated/Generated Clocks =======================================================
    Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    --------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_0       OSCInst0.OSC        OSCH                   58                     cnt2bits[27:0]      Clock Optimization not enabled
    ======================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    Summary of user generated gated clocks:
    0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 258MB peak: 258MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 258MB peak: 259MB)

    Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 258MB peak: 259MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 174MB peak: 260MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Sat Nov 15 12:11:39 2025

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Sat Nov 15 12:11:40 2025

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: V-2023.09LR-3
    Install: C:\lscc\radiant\2025.1\synpbase
    OS: Windows 10 or later
    Hostname: LPQPF559ZR1

    Implementation : impl_1
    Synopsys Lattice Technology Mapper, Version map202309lat, Build 306R, Built Mar  3 2025 21:43:36, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 199MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 199MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 200MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 203MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 254MB peak: 254MB)

    @W:BN161 : bytecounter.v(24) | Net clk_p has multiple drivers .

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 257MB peak: 257MB)

    @N:MO231 : bytecounter.v(94) | Found counter in view:work.byteCounter(verilog) instance cnt2bits[27:0]

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 258MB peak: 258MB)

    Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 258MB peak: 259MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 259MB peak: 259MB)

    @W:BN161 : bytecounter.v(24) | Net N_52 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_0 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_1 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_2 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_3 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_4 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_5 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_6 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_7 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_8 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_9 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_10 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_11 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_12 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_13 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_14 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_15 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_16 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_17 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_18 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_19 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_20 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_21 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_22 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_23 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_24 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_25 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_26 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net cntBits_3_axb_27 has multiple drivers .

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 259MB peak: 260MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 259MB peak: 260MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 259MB peak: 260MB)

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 260MB peak: 260MB)

    Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 261MB peak: 261MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:03s		    13.27ns		  19 /        58

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 261MB peak: 261MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @W:BN161 : bytecounter.v(24) | Net N_218 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_220 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_222 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_224 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_226 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_228 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_230 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_232 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_234 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_236 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_238 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_240 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_242 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_244 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_246 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_248 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_250 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_252 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_254 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_256 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_258 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_260 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_262 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_264 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_266 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_268 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_270 has multiple drivers .
    @W:BN161 : bytecounter.v(24) | Net N_272 has multiple drivers .

    Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 261MB peak: 262MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 262MB peak: 262MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:04s; Memory used current: 262MB peak: 262MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 207MB peak: 262MB)

    Writing Analyst data base C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\impl_1\synwork\byteCounter_impl_1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 262MB peak: 262MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 263MB peak: 263MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 263MB peak: 264MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 263MB peak: 264MB)

    Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 263MB peak: 264MB)

    @W:MT420 :  | Found inferred clock byteCounter|clk_p_inferred_clock with period 18.80ns. Please declare a user-defined clock on net clk_p.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Sat Nov 15 12:11:46 2025
    #

    Top view:               byteCounter
    Requested Frequency:    53.2 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl
                           C:\Workarea\Projects\LFMXO4-110-EVN\Test_Code\TestCounter_xo4_TestLED\byteCounter\impl_1\byteCounter_impl_1_cpe.ldc

    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 12.698

                                         Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                       Frequency     Frequency     Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------------------------
    byteCounter|clk_p_inferred_clock     53.2 MHz      164.0 MHz     18.797        6.099         12.698     inferred     Inferred_clkgroup_0_1
    ==========================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                          Ending                            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    byteCounter|clk_p_inferred_clock  byteCounter|clk_p_inferred_clock  |  18.797      12.698  |  No paths    -      |  No paths    -      |  No paths    -
    ===========================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: byteCounter|clk_p_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                    Starting                                                                 Arrival
    Instance        Reference                            Type        Pin     Net             Time        Slack
                    Clock
    -----------------------------------------------------------------------------------------------------------
    cnt2bits[0]     byteCounter|clk_p_inferred_clock     FD1P3DX     Q       cnt2bits[0]     1.044       12.698
    cntBits[0]      byteCounter|clk_p_inferred_clock     FD1S3DX     Q       cntBits[0]      1.044       12.698
    trigger2        byteCounter|clk_p_inferred_clock     FD1S3JX     Q       trigger2        1.044       12.698
    cnt2bits[1]     byteCounter|clk_p_inferred_clock     FD1P3DX     Q       cnt2bits[1]     1.044       12.840
    cnt2bits[2]     byteCounter|clk_p_inferred_clock     FD1P3DX     Q       cnt2bits[2]     1.044       12.840
    cntBits[1]      byteCounter|clk_p_inferred_clock     FD1S3BX     Q       cntBits[1]      1.044       12.840
    cntBits[2]      byteCounter|clk_p_inferred_clock     FD1S3BX     Q       cntBits[2]      1.044       12.840
    cnt2bits[3]     byteCounter|clk_p_inferred_clock     FD1P3DX     Q       cnt2bits[3]     1.044       12.983
    cnt2bits[4]     byteCounter|clk_p_inferred_clock     FD1P3DX     Q       cnt2bits[4]     1.044       12.983
    cntBits[3]      byteCounter|clk_p_inferred_clock     FD1S3BX     Q       cntBits[3]      1.044       12.983
    ===========================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                                    Required
    Instance         Reference                            Type        Pin     Net                Time         Slack
                     Clock
    ----------------------------------------------------------------------------------------------------------------
    cnt2bits[27]     byteCounter|clk_p_inferred_clock     FD1P3DX     D       cnt2bits_s[27]     18.691       12.698
    cntBits[27]      byteCounter|clk_p_inferred_clock     FD1S3BX     D       cntBits_3[27]      18.691       12.698
    cnt2bits[25]     byteCounter|clk_p_inferred_clock     FD1P3DX     D       cnt2bits_s[25]     18.691       12.840
    cnt2bits[26]     byteCounter|clk_p_inferred_clock     FD1P3DX     D       cnt2bits_s[26]     18.691       12.840
    cntBits[25]      byteCounter|clk_p_inferred_clock     FD1S3BX     D       cntBits_3[25]      18.691       12.840
    cntBits[26]      byteCounter|clk_p_inferred_clock     FD1S3BX     D       cntBits_3[26]      18.691       12.840
    cnt2bits[23]     byteCounter|clk_p_inferred_clock     FD1P3DX     D       cnt2bits_s[23]     18.691       12.983
    cnt2bits[24]     byteCounter|clk_p_inferred_clock     FD1P3DX     D       cnt2bits_s[24]     18.691       12.983
    cntBits[23]      byteCounter|clk_p_inferred_clock     FD1S3BX     D       cntBits_3[23]      18.691       12.983
    cntBits[24]      byteCounter|clk_p_inferred_clock     FD1S3BX     D       cntBits_3[24]      18.691       12.983
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      18.797
        - Setup time:                            0.106
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         18.691

        - Propagation time:                      5.994
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     12.698

        Number of logic level(s):                15
        Starting point:                          cnt2bits[0] / Q
        Ending point:                            cnt2bits[27] / D
        The start point is clocked by            byteCounter|clk_p_inferred_clock [rising] (rise=0.000 fall=9.398 period=18.797) on pin CK
        The end   point is clocked by            byteCounter|clk_p_inferred_clock [rising] (rise=0.000 fall=9.398 period=18.797) on pin CK

    Instance / Net                     Pin      Pin               Arrival     No. of
    Name                   Type        Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------
    cnt2bits[0]            FD1P3DX     Q        Out     1.044     1.044 r     -
    cnt2bits[0]            Net         -        -       -         -           2
    cnt2bits_cry_0[0]      CCU2D       A1       In      0.000     1.044 r     -
    cnt2bits_cry_0[0]      CCU2D       COUT     Out     1.544     2.588 r     -
    cnt2bits_cry[0]        Net         -        -       -         -           1
    cnt2bits_cry_0[1]      CCU2D       CIN      In      0.000     2.588 r     -
    cnt2bits_cry_0[1]      CCU2D       COUT     Out     0.143     2.731 r     -
    cnt2bits_cry[2]        Net         -        -       -         -           1
    cnt2bits_cry_0[3]      CCU2D       CIN      In      0.000     2.731 r     -
    cnt2bits_cry_0[3]      CCU2D       COUT     Out     0.143     2.874 r     -
    cnt2bits_cry[4]        Net         -        -       -         -           1
    cnt2bits_cry_0[5]      CCU2D       CIN      In      0.000     2.874 r     -
    cnt2bits_cry_0[5]      CCU2D       COUT     Out     0.143     3.017 r     -
    cnt2bits_cry[6]        Net         -        -       -         -           1
    cnt2bits_cry_0[7]      CCU2D       CIN      In      0.000     3.017 r     -
    cnt2bits_cry_0[7]      CCU2D       COUT     Out     0.143     3.159 r     -
    cnt2bits_cry[8]        Net         -        -       -         -           1
    cnt2bits_cry_0[9]      CCU2D       CIN      In      0.000     3.159 r     -
    cnt2bits_cry_0[9]      CCU2D       COUT     Out     0.143     3.302 r     -
    cnt2bits_cry[10]       Net         -        -       -         -           1
    cnt2bits_cry_0[11]     CCU2D       CIN      In      0.000     3.302 r     -
    cnt2bits_cry_0[11]     CCU2D       COUT     Out     0.143     3.445 r     -
    cnt2bits_cry[12]       Net         -        -       -         -           1
    cnt2bits_cry_0[13]     CCU2D       CIN      In      0.000     3.445 r     -
    cnt2bits_cry_0[13]     CCU2D       COUT     Out     0.143     3.588 r     -
    cnt2bits_cry[14]       Net         -        -       -         -           1
    cnt2bits_cry_0[15]     CCU2D       CIN      In      0.000     3.588 r     -
    cnt2bits_cry_0[15]     CCU2D       COUT     Out     0.143     3.731 r     -
    cnt2bits_cry[16]       Net         -        -       -         -           1
    cnt2bits_cry_0[17]     CCU2D       CIN      In      0.000     3.731 r     -
    cnt2bits_cry_0[17]     CCU2D       COUT     Out     0.143     3.873 r     -
    cnt2bits_cry[18]       Net         -        -       -         -           1
    cnt2bits_cry_0[19]     CCU2D       CIN      In      0.000     3.873 r     -
    cnt2bits_cry_0[19]     CCU2D       COUT     Out     0.143     4.016 r     -
    cnt2bits_cry[20]       Net         -        -       -         -           1
    cnt2bits_cry_0[21]     CCU2D       CIN      In      0.000     4.016 r     -
    cnt2bits_cry_0[21]     CCU2D       COUT     Out     0.143     4.159 r     -
    cnt2bits_cry[22]       Net         -        -       -         -           1
    cnt2bits_cry_0[23]     CCU2D       CIN      In      0.000     4.159 r     -
    cnt2bits_cry_0[23]     CCU2D       COUT     Out     0.143     4.302 r     -
    cnt2bits_cry[24]       Net         -        -       -         -           1
    cnt2bits_cry_0[25]     CCU2D       CIN      In      0.000     4.302 r     -
    cnt2bits_cry_0[25]     CCU2D       COUT     Out     0.143     4.445 r     -
    cnt2bits_cry[26]       Net         -        -       -         -           1
    cnt2bits_s_0[27]       CCU2D       CIN      In      0.000     4.445 r     -
    cnt2bits_s_0[27]       CCU2D       S0       Out     1.549     5.994 r     -
    cnt2bits_s[27]         Net         -        -       -         -           1
    cnt2bits[27]           FD1P3DX     D        In      0.000     5.994 r     -
    ====================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 264MB peak: 264MB)

    Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 264MB peak: 265MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfmxo4_9400c-5

    Register bits: 58 of 9400 (1%)
    PIC Latch:       0
    I/O cells:       9

    Details:
    CCU2D:          30
    FD1P3DX:        28
    FD1S3BX:        27
    FD1S3DX:        1
    FD1S3JX:        2
    GSR:            1
    IB:             1
    INV:            1
    OB:             8
    ORCALUT4:       20
    OSCH:           1
    PUR:            1
    VHI:            1
    VLO:            1

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 58 + 0 = 58 of 9400 (0.62%)
    Total number of LUTs: 20 + 0 = 20
    Total number of EBRs: 0 + 0 = 0 of 442 (0.00%)
    Total number of DSPs: 0 + 0 = 0 of 0 (0.00%)
    Total number of Distributed RAMs: 0 + 0 = 0
    Total number of Carry Chains: 30 + 0 = 30
    Total number of BlackBoxes: 5 + 0 = 5
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 127MB peak: 265MB)

    Process took 0h:00m:06s realtime, 0h:00m:07s cputime
    # Sat Nov 15 12:11:47 2025

    ###########################################################]

`