Testbenches Description

\testbench\qdr2_tb.v        : Qdr2 testbench ,including write and read operation;it initiates k7r321882m.v;
\testbench\k7r321882m_R04.v : SAMSUNG 32Mb QDR2-b2 SRAM Verilog Behavioral model.

Wave Description

0      ps: start;
134400 ps: Write data in Qdr2 memory;
309780 ps: Read data from Qdr2 memory;
341960 ps: Output data to Host Interface.

Function Simulation:
  (1) Click [Tools] > [ModelSim Simulator] to launch ModelSim
  (2) Change directory to "/qdr2/simulation/xp/modelsim/rtl"
  (3) Click [tools] > [Excute Macro] and select "../scripts/qdr2_fsim.tcl" to do function simulation

Timing Simulation:
  (1) Click [Tools] > [ModelSim Simulator] to launch ModelSim
  (2) Change directory to "/qdr2/simulation/xp/modelsim/timing"
  (3) Click [tools] > [Excute Macro] and select "../scripts/qdr2_tsim.tcl" to do timing simulation