library verilog;
use verilog.vl_types.all;
entity qdr_inst_PLL_PLL_QDR_1 is
    port(
        CLKI            : in     vl_logic;
        CLKFB           : in     vl_logic;
        CLKOS           : out    vl_logic;
        CLKOP           : out    vl_logic
    );
end qdr_inst_PLL_PLL_QDR_1;
