library verilog;
use verilog.vl_types.all;
entity smuxlregsre is
    port(
        D0              : in     vl_logic;
        SP              : in     vl_logic;
        CK              : in     vl_logic;
        LSR             : in     vl_logic;
        Q               : out    vl_logic
    );
end smuxlregsre;
