library verilog;
use verilog.vl_types.all;
entity moddr is
    port(
        ONEG0           : in     vl_logic;
        OPOS0           : in     vl_logic;
        CLK             : in     vl_logic;
        LSR             : in     vl_logic;
        DO              : out    vl_logic
    );
end moddr;
