library verilog;
use verilog.vl_types.all;
entity SLICE_62 is
    port(
        D0              : in     vl_logic;
        C0              : in     vl_logic;
        B0              : in     vl_logic;
        A0              : in     vl_logic;
        DI0             : in     vl_logic;
        CLK             : in     vl_logic;
        F0              : out    vl_logic;
        Q0              : out    vl_logic
    );
end SLICE_62;
