library verilog;
use verilog.vl_types.all;
entity qdrSA_16_MGIOL is
    port(
        IOLDO           : out    vl_logic;
        CLK             : in     vl_logic;
        ONEG0           : in     vl_logic;
        OPOS0           : in     vl_logic
    );
end qdrSA_16_MGIOL;
