library verilog;
use verilog.vl_types.all;
entity EHXPLLB0012 is
    port(
        RST             : in     vl_logic;
        CLKI            : in     vl_logic;
        CLKFB           : in     vl_logic;
        DDAMODE         : in     vl_logic;
        DDAIZR          : in     vl_logic;
        DDAILAG         : in     vl_logic;
        DDAIDEL0        : in     vl_logic;
        DDAIDEL1        : in     vl_logic;
        DDAIDEL2        : in     vl_logic;
        CLKOP           : out    vl_logic;
        CLKOS           : out    vl_logic;
        CLKOK           : out    vl_logic;
        LOCK            : out    vl_logic;
        DDAOZR          : out    vl_logic;
        DDAOLAG         : out    vl_logic;
        DDAODEL0        : out    vl_logic;
        DDAODEL1        : out    vl_logic;
        DDAODEL2        : out    vl_logic
    );
end EHXPLLB0012;
