// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2004 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
//
//                     TEL: 1-800-Lattice (USA and Canada)
//                          408-826-6000 (other locations)
//
//                     web: http://www.latticesemi.com/
//                     email: techsupport@latticesemi.com
//
// --------------------------------------------------------------------
//
//  Project:           QDR-II Memory Controller
//  File:              pipeline.v
//  Title:             pipeline
//  Description:       This is an optional pipeline module for
//                     performance improvement.  If the host is
//                     implemented inside the FPGA, this module may be
//                     removed.
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// $Log: pipeline.v,v $
// Revision 1.0  2004-01-15 11:30:50-08  jhsin
// Initial revision
//
//
// --------------------------------------------------------------------

// -----------------------------------------------------------------------------
// Host interface pipeline (This is for performance improvement and may not be
//                          needed if the host is implemented in FPGA.)
//
//   hostWA[] \       ______       ______       ______       / hWA[]
//   hostRA[] | ---->|      |---->|      |---->|      |----> | hRA[]
//   hostWD[] |      | DFFs |     | DFFs |     | DFFs |      | hWD[]
//   hostWP[] |      |      |     |      |     |      |      | hWP[]
//   hostRN   |   +--|>     |  +--|>     |  +--|>     |      | hRN
//   hostWN   |   |  |______|  |  |______|  |  |______|      | hWN
//   host16   |   |            |            |                | h16
//   host08   /   hostCLK      hostCLK      hostCLK          \ h08
//
//              \       ______       ______       ______       /
//   hostRQ[]   | <----|      |<----|      |<----|      |<---- | hRQ[]
//   hostPERR[] |      | DFFs |     | DFFs |     | DFFs |      | hPERR[]
//              /      |      |     |      |     |      |      \
//                     |     <|--+  |     <|--+  |     <|--+
//                     |______|  |  |______|  |  |______|  |
//                               |            |            |
//                               cqCLK        cqCLK        cqCLK
//
// -----------------------------------------------------------------------------

`timescale 1ns/1ps

module pipeline(
   // Input pipeline
   inclk,
   hostWA,
   hostRA,
   hostWD,
   hostWP,
   hostRN,
   hostWN,
   host16,
   host08,
   hWA,
   hRA,
   hWD,
   hWP,
   hRN,
   hWN,
   h16,
   h08,
   // Output pipeline
   outclk,
   hRQ,
   hPERR,
   hostRQ,
   hostPERR
);

input         inclk;

input  [21:0] hostWA;
input  [21:0] hostRA;
input  [31:0] hostWD;
input  [ 3:0] hostWP;
input         hostRN;
input         hostWN;
input         host16;
input         host08;
output [21:0] hWA;
output [21:0] hRA;
output [31:0] hWD;
output [ 3:0] hWP;
output        hRN;
output        hWN;
output        h16;
output        h08;

input         outclk;

input  [31:0] hRQ;
input  [ 3:0] hPERR;
output [31:0] hostRQ;
output [ 3:0] hostPERR;

reg    [21:0] hWA0, hWA1, hWA;
reg    [21:0] hRA0, hRA1, hRA;
reg    [31:0] hWD0, hWD1, hWD;
reg    [ 3:0] hWP0, hWP1, hWP;
reg           hRN0, hRN1, hRN;
reg           hWN0, hWN1, hWN;
reg           h160, h161, h16;
reg           h080, h081, h08;

reg    [31:0] hRQ0, hRQ1;
reg    [31:0] hostRQ/* synthesis dout="" */;
reg    [ 3:0] hPERR0, hPERR1;
reg    [ 3:0] hostPERR;

// -----------------------------------------------------------------------------
// input pipelining
// -----------------------------------------------------------------------------

always @(posedge inclk) begin
   hWA0   <= hostWA;
   hWA1   <= hWA0;
   hWA    <= hWA1;
end

always @(posedge inclk) begin
   hRA0   <= hostRA;
   hRA1   <= hRA0;
   hRA    <= hRA1;
end

always @(posedge inclk) begin
   hWD0   <= hostWD;
   hWD1   <= hWD0;
   hWD    <= hWD1;
end

always @(posedge inclk) begin
   hWP0   <= hostWP;
   hWP1   <= hWP0;
   hWP    <= hWP1;
end

always @(posedge inclk) begin
   hRN0   <= hostRN;
   hRN1   <= hRN0;
   hRN    <= hRN1;
end

always @(posedge inclk) begin
   hWN0   <= hostWN;
   hWN1   <= hWN0;
   hWN    <= hWN1;
end

always @(posedge inclk) begin
   h160   <= host16;
   h161   <= h160;
   h16    <= h161;
end

always @(posedge inclk) begin
   h080   <= host08;
   h081   <= h080;
   h08    <= h081;
end

// -----------------------------------------------------------------------------
// output pipelining
// -----------------------------------------------------------------------------

always @(posedge outclk) begin
   hRQ0   <= hRQ;
   hRQ1   <= hRQ0;
   hostRQ <= hRQ1;
end

always @(posedge outclk) begin
   hPERR0   <= hPERR;
   hPERR1   <= hPERR0;
   hostPERR <= hPERR1;
end

//------------------------------------------------------------------------------

endmodule
