library verilog;
use verilog.vl_types.all;
entity pipeline is
    port(
        inclk           : in     vl_logic;
        hostWA          : in     vl_logic_vector(21 downto 0);
        hostRA          : in     vl_logic_vector(21 downto 0);
        hostWD          : in     vl_logic_vector(31 downto 0);
        hostWP          : in     vl_logic_vector(3 downto 0);
        hostRN          : in     vl_logic;
        hostWN          : in     vl_logic;
        host16          : in     vl_logic;
        host08          : in     vl_logic;
        hWA             : out    vl_logic_vector(21 downto 0);
        hRA             : out    vl_logic_vector(21 downto 0);
        hWD             : out    vl_logic_vector(31 downto 0);
        hWP             : out    vl_logic_vector(3 downto 0);
        hRN             : out    vl_logic;
        hWN             : out    vl_logic;
        h16             : out    vl_logic;
        h08             : out    vl_logic;
        outclk          : in     vl_logic;
        hRQ             : in     vl_logic_vector(31 downto 0);
        hPERR           : in     vl_logic_vector(3 downto 0);
        hostRQ          : out    vl_logic_vector(31 downto 0);
        hostPERR        : out    vl_logic_vector(3 downto 0)
    );
end pipeline;
