library verilog;
use verilog.vl_types.all;
entity qdr2 is
    port(
        hostCLK         : in     vl_logic;
        hostWA          : in     vl_logic_vector(21 downto 0);
        hostRA          : in     vl_logic_vector(21 downto 0);
        hostWD          : in     vl_logic_vector(31 downto 0);
        hostWP          : in     vl_logic_vector(3 downto 0);
        hostRN          : in     vl_logic;
        hostWN          : in     vl_logic;
        host16          : in     vl_logic;
        host08          : in     vl_logic;
        hostRQ          : out    vl_logic_vector(31 downto 0);
        hostPERR        : out    vl_logic_vector(3 downto 0);
        qdrCQ           : in     vl_logic;
        qdrQ            : in     vl_logic_vector(15 downto 0);
        qdrPQ           : in     vl_logic_vector(1 downto 0);
        qdrK            : out    vl_logic;
        qdrKN           : out    vl_logic;
        qdrRN           : out    vl_logic;
        qdrWN           : out    vl_logic;
        qdrSA           : out    vl_logic_vector(19 downto 0);
        qdrD            : out    vl_logic_vector(15 downto 0);
        qdrPD           : out    vl_logic_vector(1 downto 0);
        qdrBWN          : out    vl_logic_vector(1 downto 0)
    );
end qdr2;
