library verilog;
use verilog.vl_types.all;
entity k7r321882m is
    generic(
        addr_bits       : integer := 20;
        data_bits       : integer := 18;
        mem_sizes       : integer := 2097151;
        qdelay          : real    := 0.380000;
        aor_r           : integer := 0;
        aor_w           : integer := 1;
        dor_r           : integer := 2;
        dor_w           : integer := 0;
        bu_n            : integer := 2
    );
    port(
        D               : in     vl_logic_vector;
        Q               : out    vl_logic_vector;
        SA              : in     vl_logic_vector;
        R_N             : in     vl_logic;
        W_N             : in     vl_logic;
        BW_N            : in     vl_logic_vector(1 downto 0);
        K               : in     vl_logic;
        K_N             : in     vl_logic;
        C               : in     vl_logic;
        C_N             : in     vl_logic;
        CQ              : out    vl_logic;
        CQ_N            : out    vl_logic;
        DOFF_N          : in     vl_logic
    );
end k7r321882m;
