library verilog;
use verilog.vl_types.all;
entity PLL_QDR is
    port(
        hostCLK         : in     vl_logic;
        qdrCQ           : in     vl_logic;
        clk4out         : out    vl_logic;
        clk4qdrK        : out    vl_logic;
        cqCLK           : out    vl_logic
    );
end PLL_QDR;
