library verilog;
use verilog.vl_types.all;
entity SLICE_90 is
    port(
        M1              : in     vl_logic;
        M0              : in     vl_logic;
        CLK             : in     vl_logic;
        Q0              : out    vl_logic;
        Q1              : out    vl_logic
    );
end SLICE_90;
