library verilog;
use verilog.vl_types.all;
entity ODDR_XP is
    port(
        clk             : in     vl_logic;
        din_a           : in     vl_logic_vector(3 downto 0);
        din_b           : in     vl_logic_vector(3 downto 0);
        dout            : out    vl_logic_vector(3 downto 0)
    );
end ODDR_XP;
