// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2004 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in  for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
//
//                     TEL: 1-800-Lattice (USA and Canada)
//                          408-826-6000 (other locations)
//
//                     web: http://www.latticesemi.com/
//                     email: techsupport@latticesemi.com
//
// --------------------------------------------------------------------
//
//  Project:           QDR-II Memory Controller
//  File:              pll_qdr.v
//  Title:             pll_qdr
//  Description:       Main module of the controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// $Log: pll_qdr.v,v $
// Revision 1.0  2004-01-15 11:30:50-08  jhsin
// Initial revision
//
//
// --------------------------------------------------------------------

`timescale 1ns/1ps

module PLL_QDR(
				hostCLK,
				qdrCQ,
				clk4out,
				clk4qdrK,
				cqCLK
				);

input			hostCLK;
input			qdrCQ;
output		clk4out;
output		clk4qdrK;
output		cqCLK;


defparam PLL_QDR_0.FIN = "178";
defparam PLL_QDR_0.CLKFB_DIV = "1";
defparam PLL_QDR_0.CLKI_DIV = "1";
defparam PLL_QDR_0.CLKOP_DIV = "1";
defparam PLL_QDR_0.CLKOK_DIV = "2";
defparam PLL_QDR_0.DELAY_CNTL = "STATIC";
defparam PLL_QDR_0.FDEL = "0";
defparam PLL_QDR_0.WAKE_ON_LOCK = "OFF";
defparam PLL_QDR_0.PHASEADJ = "90";
defparam PLL_QDR_0.DUTY = "4";

EHXPLLB PLL_QDR_0(
                .RST            (1'b0       ),
                .CLKI           (hostCLK    ),
                .CLKFB          (clk4out    ),
                .DDAMODE        (1'b0       ),
                .DDAIZR         (1'b0       ),
                .DDAILAG        (1'b0       ),
                .DDAIDEL0       (1'b0       ),
                .DDAIDEL1       (1'b0       ),
                .DDAIDEL2       (1'b0       ),
                .CLKOP          (clk4out    ),
                .CLKOK          (           ),
                .CLKOS          (clk4qdrK   ),
                .LOCK           (           ),
                .DDAOZR         (           ),
                .DDAOLAG        (           ),
                .DDAODEL0       (           ),
                .DDAODEL1       (           ),
                .DDAODEL2       (           )
            );


// -----------------------------------------------------------------------------
// Clock for reading QDR data
// -----------------------------------------------------------------------------

defparam PLL_QDR_1.FIN = "178";
defparam PLL_QDR_1.CLKFB_DIV = "1";
defparam PLL_QDR_1.CLKI_DIV = "1";
defparam PLL_QDR_1.CLKOP_DIV = "1";
defparam PLL_QDR_1.CLKOK_DIV = "2";
defparam PLL_QDR_1.DELAY_CNTL = "STATIC";
defparam PLL_QDR_1.FDEL = "0";
defparam PLL_QDR_1.WAKE_ON_LOCK = "OFF";
defparam PLL_QDR_1.PHASEADJ = "90";
defparam PLL_QDR_1.DUTY = "4";
wire    fb_pll_qdr1;

EHXPLLB PLL_QDR_1(
                .RST            (1'b0       ),
                .CLKI           (qdrCQ      ),
                .CLKFB          (fb_pll_dqr1),
                .DDAMODE        (1'b0       ),
                .DDAIZR         (1'b0       ),
                .DDAILAG        (1'b0       ),
                .DDAIDEL0       (1'b0       ),
                .DDAIDEL1       (1'b0       ),
                .DDAIDEL2       (1'b0       ),
                .CLKOP          (fb_pll_dqr1),
                .CLKOK          (           ),
                .CLKOS          (cqCLK      ),
                .LOCK           (           ),
                .DDAOZR         (           ),
                .DDAOLAG        (           ),
                .DDAODEL0       (           ),
                .DDAODEL1       (           ),
                .DDAODEL2       (           )
            );

endmodule
