DisplayPort to PCIe Reference Design and Demonstration

Transferring DisplayPort Video Data to a Computer through PCIe with a Direct Memory Access Engine

The CertusPro™-NX DisplayPort (DP) to Peripheral Component Interconnect Express (PCIe®) reference design demonstrates the functionality of transferring DisplayPort video data to a computer through PCIe Gen3x4 with a Direct Memory Access (DMA) engine. This reference design is based on the CertusPro-NX PCIe Vision Board RevA (LFCPNX-PCIEV-EVN_REVA) and runs on Linux® operating system (OS) with driver supporting video data transfer at different resolutions. The application software renders the video data on the monitor.

Features

  • The Lattice DisplayPort IP supports four lanes and lane rates up to 5.4 Gbps, handshaking with the upstream DisplayPort source and video pipeline components to decode the video data from the main link transport and output through Unified Video Streaming Interface (UVSI).
  • The Unified Video to PCIe Bridge maps UVSI packets to PCIe DMA AXI-S packets.
  • The Lattice PCIe x4 IP provides Direct Memory Access (DMA) engine to perform data transfer between FPGA and host PC.

Jump to

Block Diagram

DisplayPort to PCIe Reference Design Block Diagram

Documentation

下载
标题编号版本日期格式文件大小
选择全部
DisplayPort to PCIe Reference Design and Demonstration Documentation
To learn more about this product design and to access the complete source code, bitstream and user guide in GitHub, please click here
1/30/2026WEB