Lattice OCP Ready Solutions for DC-SCM and HPM CPLD Connectivity

Empowering Interoperable, Scalable, and Low-Power Server Management

Lattice Semiconductor offers cutting-edge IP cores and reference designs—LTPI (LVDS Tunneling Protocol & Interface) and MPESTI (Modular Peripheral Sideband Tunneling Interface)—that are fully compliant with OCP DC-SCM 2.0/2.1 specifications, enabling seamless connectivity between Secure Control Modules (SCM) and Host Processor Modules (HPM).

Key Features

OCP Compliant
Aligns with DC-SCM 2.0/2.1 standards

Modular & Scalable
Enables flexible, optimized resource; server design and upgrades

Secure & Resilient
Root of Trust (RoT) implementations

Validated Ecosystem
Proven interoperability with major server vendors

Block Diagram

放大图片

DC-SCM 2.0 LVDS Tunneling Protocol & Interface (LTPI) Block Diagram

Videos

OCP Overview
LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough Guide
LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough
Virtual Laboratory for Remote Demonstration
Dual Host Processor Module (HPM) and Single Secure Control Module (SCM) Proof of Concept Demo
Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI)
Intel Lincoln City Reference Architecture with Lattice FPGAs

IP Cores

IP Core
 ​​eSPI Target IP核​ 莱迪思eSPI Target IP核符合英特尔eSPI规范，且在用户界面中拥有自己的虚拟线通道。
MachXO5-NX, Mach-NX, MachXO3D, MachXO3, MachXO2, MachXO4 
APB, AHB-Lite, Lattice Sentry, OCP 
IP Core
 ​​M-PESTI Initiator IP核 莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。
Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
MPESTI, UART, APB, Lattice Sentry, OCP 
IP Core
 DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX, MachXO4 
CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 

Reference Designs

Reference Design
 Lattice Sentry 4.0 SCM和HPM CPLD参考设计 这是一个Sentry 4.0服务器解决方案平台的安全控制模块（SCM）和主机平台模块（HPM）的CPLD设计模板。
MachXO3D, MachXO5-NX 
SCM, HPM, CPLD, Lattice Sentry, Security, Defense, LTPI, MPESTI, SGPIO, eSPI, OCP 
Reference Design
 MPESTI Initiator Reference Design The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.
Avant-E, MachXO5-NX, MachXO3, MachXO3D 
MPESTI, UART, APB, AHB, RISC-V, OCP 
Reference Design
 LVDS Tunneling Protocol and Interface Reference Design The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 

Documentation

快速参考

技术资源

Reference Design

标题	编号	版本	日期	格式	文件大小
选择全部
LTPI Hardware Checklist	FPGA-TN-02417	1.0	10/7/2025	PDF	521.6 KB
LTPI Quick Start Guide	FPGA-AN-02108	1.0	10/7/2025	PDF	1 MB

标题	编号	版本	日期	格式	文件大小
选择全部
DC-SCM LTPI IP (Legacy) - User Guide	FPGA-IPUG-02200	2.2	5/6/2026	PDF	1.7 MB
eSPI Target IP Core - User Guide	FPGA-IPUG-02260	1.3	6/26/2026	PDF	1.5 MB
M-PESTI Initiator IP Core - User Guide	FPGA-IPUG-02258	1.6	6/26/2026	PDF	2.3 MB

标题	编号	版本	日期	格式	文件大小
选择全部
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – Source Code			9/5/2024	ZIP	86 MB
LVDS Tunneling Protocol and Interface Reference Design – Source Code			6/16/2026	ZIP	1.1 GB
LVDS Tunneling Protocol and Interface Reference Design – User Guide	FPGA-RD-02247	1.6	6/15/2026
MachXO3D Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – User Guide	FPGA-UG-02222	1.0	10/28/2025	PDF	4.9 MB
MPESTI Initiator Reference Design – Source Code			4/4/2025	ZIP	15.7 MB
MPESTI Initiator Reference Design – User Guide	FPGA-RD-02312	1.1	11/21/2025	PDF	3 MB