LatticeECP3

高效,适用于创新,采用小尺寸的紧凑型封装

非常高效的性能——在尽可能小的空间内实现所有功能是至关重要的,拥有150K LUT的LatticeECP3可满足您的需求

最大的可靠性,最低的成本和功耗——LatticeECP3 FPGA带有片上SERDES以及低至0.5W的功耗,助您提高工业、远程通信或车用设备的可靠性并且降低成本

易于互连的FPGA——使用合适协议的SERDES,合适接口的I/O,使用LatticeECP3满足您的系统连接和扩展需求

特性

  • 多达16个通道,速率为3.125 Gbps
  • 800 Mbps DDR3,1Gbps LVDS
  • 多达586个可编程sysIO缓冲器,支持PCI Express、以太网(GbE、XAUI & SGMII)、HDMI、SMPTE、串行Rapid I/O、CPRI和JESD204A/B等等
  • 高达150K LUT以及6.8 Mbit的SRAM
  • 多种封装选择,尺寸小至10.0 mm x 10.0 mm,功耗低至0.5 W以下

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产品系列表

LatticeECP3 器件选型指南

参数 ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150
LUT (K) 17 33 67 92 149
EBR SRAM 块 38 72 240 240 372
EBR SRAM (Kbit) 700 1327 4420 4420 6850
分布式RAM (Kbit) 36 68 145 188 303
18 x 18 乘法器 24 64 128 128 320
3.2 Gbps SERDES 通道 4 4 12 12 16
PLL + DLL 2+2 4+2 10+2 10+2 10+2
DDR 支持 DDR3 800, DDR2 533, DDR 400
引导闪存 外部 外部 外部 外部 外部
双引导
位流加密
内核电压 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
Temp C
Temp I
Temp AEC-Q100 - - -
0.5 mm 引脚间距 I/O 数量 / SERDES
  ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150
328-ball csBGA (10 x 10 mm) 116 / 2
1.0 mm 引脚间距 I/O 数量 / SERDES
  ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150
256-ball ftBGA (17 x 17 mm) 133 / 4 133 / 4
484-ball fpBGA (23 x 23 mm) 222 / 4 295 / 4 295 / 4 295 / 4
672-ball fpBGA (27 x 27 mm) 310 / 4 380 / 8 380 / 8 380 / 8
1156-ball fpBGA (35 x 35 mm) 490 / 12 490 / 12 586 / 16

莱迪思车用(AEC-Q100认证) LatticeECP3 器件选型指南

参数 LA-ECP3-17 LA-ECP3-35
LUT (K) 17 33
EBR SRAM (Kbit) 700 1327
EBR SRAM 块 38 72
分布式RAM (Kbit) 36 68
18 x 18 乘法器 24 64
3.2 Gbps SERDES 通道 4 4
最多可用 I/O 222 310
PLL + DLL 2+2 4+2
0.5 mm 引脚间距 I/O 数量 / SERDES
  LA-ECP3-17 LA-ECP3-35
328-ball csBGA (10 x 10 mm) 116 / 2
1.0 mm 引脚间距 I/O 数量 / SERDES
  LA-ECP3-17 LA-ECP3-35
256-ball ftBGA (17 x 17 mm) 133 / 4 133 / 4
484-ball fpBGA (23 x 23 mm) 222 / 4 295 / 4
672-ball fpBGA (27 x 27 mm) 310 / 4

解决方案实例

解决网络边缘的连接问题

  • 构建低成本的以太网与定制或传统接口之间的桥接
  • 快速实现ASSP与无线基站中常见协议之间的桥接,包括CPRI和JESD204
  • 实现网络流量的预处理,通过减少处理器的工作量来提高性能
  • 通过分担DSP功能来增强pico和femto-cell中ASSP的性能

实现高性能的控制面板解决方案,适用于通信、工业、医疗和其他应用

  • 使用串行接口提供与系统其他模块之间的高性能接口
  • 通过优化的预处理算法,减轻控制处理器的工作量

通过超快、大批量并行的工程实现,增强图片/视频系统性能

  • 使用业界领先的功能,提高图像质量
  • 通过成熟的视频分析功能快速解决现实世界的问题
  • 提供与常用的视频协议之间的接口

构建创新的汽车解决方案

  • 实现低成本的串行接口,在整个汽车内部传输图像数据
  • 使用硬件实现,高效地分析图像数据
  • 通过分担显示的缩放、旋转和组合功能,减少处理器的工作量

设计资源

IP和参考设计

使用经过预先测试、可重复使用的功能简化您的设计工作

软件

覆盖整个设计流程,非常易于使用

开发套件和开发板

我们的开发板和开发套件能够简化您的设计流程

编程硬件

使用我们的编程硬件,轻松完成在系统编程和在线重配置

文档

快速参考
技术资源
资讯资源
下载
标题编号版本日期格式文件大小
选择全部
Advanced Security Encryption Key Programming Guide for ECP Device Family
FPGA-TN-022021.87/22/2024PDF2.2 MB
ECP3 migration 17to35_256
1.24/6/2012XLS68 KB
ECP3 migration 17to35_484
1.24/6/2012XLS62 KB
ECP3 migration 17to70_484
1.24/6/2012XLS67 KB
ECP3 migration 17to95_484
1.24/6/2012XLS67 KB
ECP3 migration 35to150_672
1.17/9/2009XLS87.5 KB
ECP3 migration 35to70_484
1.29/10/2012XLS85.5 KB
ECP3 migration 35to70_672
1.29/10/2012XLS96 KB
ECP3 migration 35to95_484
1.29/10/2012XLS86 KB
ECP3 migration 35to95_672
1.29/10/2012XLS96.5 KB
ECP3 migration 70to150_1156
1.29/10/2012XLS127.5 KB
ECP3 migration 70to150_672
1.29/10/2012XLS97.5 KB
ECP3 migration 70to95_1156
1.17/9/2009XLS14.5 KB
ECP3 migration 70to95_484
1.17/9/2009XLS14.5 KB
ECP3 migration 70to95_672
1.17/9/2009XLS15 KB
ECP3 migration 95to150_1156
1.29/10/2012XLS127.5 KB
ECP3 migration 95to150_672
1.29/10/2012XLS97.5 KB
Electrical Recommendations for Lattice SERDES
FPGA-TN-020773.312/16/2025PDF1.2 MB
High-Speed PCB Design Considerations
FPGA-TN-021786.48/21/2024PDF3.5 MB
LA-LatticeECP3 Automotive Family Data Sheet
FPGA-DS-020521.37/20/2021PDF4.3 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.16/26/2026ZIP3.3 MB
LatticeECP3 and Broadcom 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN12171.07/26/2010PDF1.5 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN12181.12/13/2012PDF3.5 MB
LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements
TN11491.510/7/2013PDF3.8 MB
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN12191.07/26/2010PDF1.4 MB
LatticeECP3 Family Data Sheet
FPGA-DS-020743.41/5/2026PDF2.9 MB
LatticeECP3 Hardware Checklist
FPGA-TN-021832.411/5/2025PDF793.8 KB
LatticeECP3 High-Speed I/O Interface
FPGA-TN-021842.66/2/2023PDF4.9 MB
LatticeECP3 Marvell 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN11961.12/13/2012PDF2.9 MB
LatticeECP3 Marvell SGMII Physical/MAC Layer Interoperability
TN11971.12/13/2012PDF3 MB
LatticeECP3 Marvell XAUI 10 Gbps Physical Layer Interoperability
TN11941.12/13/2012PDF2.7 MB
LatticeECP3 Memory Usage Guide
FPGA-TN-021882.08/5/2025PDF1.4 MB
LatticeECP3 Power Consumption and Management
FPGA-TN-021891.25/23/2023PDF386.3 KB
LatticeECP3 SERDES/PCS Reset Sequence - Source Code
For use with Technical Note - FPGA-TN-02190
FPGA-TN-021901.26/29/2022ZIP5.6 KB
LatticeECP3 SERDES/PCS Usage Guide
FPGA-TN-021903.06/4/2024PDF3.3 MB
LatticeECP3 Slave SPI Port User Guide
FPGA-TN-021361.98/19/2021PDF1.3 MB
LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide
FPGA-TN-021912.79/24/2021PDF2.3 MB
LatticeECP3 sysCONFIG Usage Guide
FPGA-TN-021923.510/24/2025PDF1.8 MB
LatticeECP3 sysDSP Usage Guide
FPGA-TN-021931.43/20/2024PDF3.1 MB
LatticeECP3 sysIO Usage Guide
FPGA-TN-021942.411/5/2025PDF972.9 KB
LatticeECP3-150EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.54/15/2010CSV43.8 KB
LatticeECP3-17EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.61/24/2012CSV23.9 KB
LatticeECP3-35EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.44/15/2010CSV29 KB
LatticeECP3-70E Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.27/13/2009CSV49.8 KB
LatticeECP3-70EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.34/15/2010CSV49.1 KB
LatticeECP3-95E Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.27/9/2009CSV49.8 KB
LatticeECP3-95EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.24/15/2010CSV49 KB
LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature
FPGA-TN-022031.810/26/2021PDF1.3 MB
Low-Cost Serial RapidIO to TI 6482 Digital Signal Processor Interoperability with LatticeECP3
TN12141.110/18/2010PDF176.4 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Package Diagrams
FPGA-DS-020538.87/14/2026PDF9.6 MB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN80771.31/4/2013RAR1.4 MB
Soft Error Detection SED Usage Guide
FPGA-TN-022072.05/31/2022PDF815.1 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.35/6/2026PDF753.9 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Transmission of High-Speed Serial Signals over Common Cable Media
FPGA-TN-021961.98/6/2023PDF1.8 MB
标题编号版本日期格式文件大小
选择全部
LA-LatticeECP3 Automotive Family Data Sheet
FPGA-DS-020521.37/20/2021PDF4.3 MB
LatticeECP3 Family Data Sheet
FPGA-DS-020743.41/5/2026PDF2.9 MB
标题编号版本日期格式文件大小
选择全部
Advanced Security Encryption Key Programming Guide for ECP Device Family
FPGA-TN-022021.87/22/2024PDF2.2 MB
Electrical Recommendations for Lattice SERDES
FPGA-TN-020773.312/16/2025PDF1.2 MB
Electrical Recommendations for Lattice SERDES (Chinese Language Version)
TN1114C02.810/12/2012PDF2 MB
High-Speed PCB Design Considerations
FPGA-TN-021786.48/21/2024PDF3.5 MB
High-Speed PCB Design Considerations (Chinese Language Version)
TN1033C06.15/23/2011PDF434.6 KB
LatticeECP3 and Broadcom 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN12171.07/26/2010PDF1.5 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN12181.12/13/2012PDF3.5 MB
LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements
TN11491.510/7/2013PDF3.8 MB
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN12191.07/26/2010PDF1.4 MB
LatticeECP3 Hardware Checklist
FPGA-TN-021832.411/5/2025PDF793.8 KB
LatticeECP3 High-Speed I/O Interface
FPGA-TN-021842.66/2/2023PDF4.9 MB
LatticeECP3 Marvell 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
TN11961.12/13/2012PDF2.9 MB
LatticeECP3 Marvell SGMII Physical/MAC Layer Interoperability
TN11971.12/13/2012PDF3 MB
LatticeECP3 Marvell XAUI 10 Gbps Physical Layer Interoperability
TN11941.12/13/2012PDF2.7 MB
LatticeECP3 Memory Usage Guide
FPGA-TN-021882.08/5/2025PDF1.4 MB
LatticeECP3 Power Consumption and Management
FPGA-TN-021891.25/23/2023PDF386.3 KB
LatticeECP3 SERDES/PCS Reset Sequence - Source Code
For use with Technical Note - FPGA-TN-02190
FPGA-TN-021901.26/29/2022ZIP5.6 KB
LatticeECP3 SERDES/PCS Usage Guide
FPGA-TN-021903.06/4/2024PDF3.3 MB
LatticeECP3 SERDES/PCS Usage Guide (Chinese Language Version)
TN1176C02.48/28/2012PDF8.7 MB
LatticeECP3 SERDES/PCS Usage Guide (Japanese Language Version)
TN1176J2.48/22/2012PDF2.7 MB
LatticeECP3 Slave SPI Port User Guide
FPGA-TN-021361.98/19/2021PDF1.3 MB
LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide
FPGA-TN-021912.79/24/2021PDF2.3 MB
LatticeECP3 sysCONFIG Usage Guide
FPGA-TN-021923.510/24/2025PDF1.8 MB
LatticeECP3 sysDSP Usage Guide
FPGA-TN-021931.43/20/2024PDF3.1 MB
LatticeECP3 sysIO Usage Guide
FPGA-TN-021942.411/5/2025PDF972.9 KB
LatticeECP3 sysIO Usage Guide (Chinese Language Version)
TN1177C02.06/26/2012PDF3.1 MB
LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature
FPGA-TN-022031.810/26/2021PDF1.3 MB
Low-Cost Serial RapidIO to TI 6482 Digital Signal Processor Interoperability with LatticeECP3
TN12141.110/18/2010PDF176.4 KB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-020811.27/15/2026PDF2.8 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN80771.31/4/2013RAR1.4 MB
Soft Error Detection SED Usage Guide
FPGA-TN-022072.05/31/2022PDF815.1 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.35/6/2026PDF753.9 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Transmission of High-Speed Serial Signals over Common Cable Media
FPGA-TN-021961.98/6/2023PDF1.8 MB
标题编号版本日期格式文件大小
选择全部
ECP3 migration 17to35_256
1.24/6/2012XLS68 KB
ECP3 migration 17to35_484
1.24/6/2012XLS62 KB
ECP3 migration 17to70_484
1.24/6/2012XLS67 KB
ECP3 migration 17to95_484
1.24/6/2012XLS67 KB
ECP3 migration 35to150_672
1.17/9/2009XLS87.5 KB
ECP3 migration 35to70_484
1.29/10/2012XLS85.5 KB
ECP3 migration 35to70_672
1.29/10/2012XLS96 KB
ECP3 migration 35to95_484
1.29/10/2012XLS86 KB
ECP3 migration 35to95_672
1.29/10/2012XLS96.5 KB
ECP3 migration 70to150_1156
1.29/10/2012XLS127.5 KB
ECP3 migration 70to150_672
1.29/10/2012XLS97.5 KB
ECP3 migration 70to95_1156
1.17/9/2009XLS14.5 KB
ECP3 migration 70to95_484
1.17/9/2009XLS14.5 KB
ECP3 migration 70to95_672
1.17/9/2009XLS15 KB
ECP3 migration 95to150_1156
1.29/10/2012XLS127.5 KB
ECP3 migration 95to150_672
1.29/10/2012XLS97.5 KB
LatticeECP3-150EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.54/15/2010CSV43.8 KB
LatticeECP3-17EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.61/24/2012CSV23.9 KB
LatticeECP3-35EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.44/15/2010CSV29 KB
LatticeECP3-70E Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.27/13/2009CSV49.8 KB
LatticeECP3-70EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.34/15/2010CSV49.1 KB
LatticeECP3-95E Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.27/9/2009CSV49.8 KB
LatticeECP3-95EA Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.24/15/2010CSV49 KB
Package Diagrams
FPGA-DS-020538.87/14/2026PDF9.6 MB
标题编号版本日期格式文件大小
选择全部
DDR2 Demo for the LatticeECP3 Serial Protocol Board
Describes the DDR2 Demo for use with the LatticeECP3 Serial Protocol Board.
UG495/22/2013PDF346 KB
JESD207 IP Core User's Guide
IPUG1111.08/27/2013PDF2.4 MB
LatticeECP3 AMC Evaluation Board User's Guide
EB5601.18/27/2012PDF6.6 MB
LatticeECP3 AMC Serial RapidIO 2.1 Demo User's Guide
UG3901.011/17/2010PDF2.7 MB
LatticeECP3 CPRI Demo Design User's Guide
UG2601.25/3/2012PDF2.7 MB
LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide
UG3801.46/8/2012PDF2.7 MB
LatticeECP3 Eye/Backplane Demo for the LatticeECP3 Serial I/O Protocol Board User's Guide
UG2401.43/4/2011PDF849.9 KB
LatticeECP3 PCI Express Root Complex Lite x1 Native Demo
UG401.010/29/2010PDF263.2 KB
LatticeECP3 Serial Protocol Board - Revision D User's Guide
EB441.37/8/2010PDF2.4 MB
LatticeECP3 Video Protocol Board - Revision B User's Guide
EB391.33/2/2010PDF2.5 MB
LatticeECP3 XAUI Demo
UG2301.36/16/2011PDF1.1 MB
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2
IPUG189.211/8/2010PDF4.6 MB
PCIe Sample Demo Debugging and Packet Analysis Guide
TN127110/13/2013PDF3.7 MB
RapidIO 2.x LP-Serial Physical Layer Endpoint IP Core User's Guide
IPUG8401.36/28/2011PDF2.4 MB
Tri-Rate SDI PHY IP Loopback and Passthrough Sample Designs
UG221.110/30/2009PDF222.2 KB
Tri-Rate SMPTE SDI Demo
UG2101.512/21/2011PDF1.1 MB
标题编号版本日期格式文件大小
选择全部
MDIO (Management Data Input/Output Interface) Peripheral - WISHBONE Compatible
FPGA-RD-021301.21/31/2021PDF1021 KB
MIPI CSI-2-to-CMOS Parallel Sensor Bridge
RD11461.412/28/2016ZIP4.3 MB
MIPI CSI2-to-CMOS Parallel Sensor Bridge - Documentation
FPGA-RD-021311.61/31/2021PDF1.4 MB
Parallel to MIPI CSI-2 TX Bridge - Documentation
FPGA-RD-021321.68/19/2021PDF1.1 MB
Parallel to MIPI CSI-2 TX Bridge - Source Code
RD11831.51/1/2015ZIP1.2 MB
Parallel to MIPI DSI TX Bridge - Documentation
FPGA-RD-021331.61/31/2021PDF1.2 MB
Parallel to MIPI DSI TX Bridge - Source Code
RD11841.51/1/2015ZIP2.6 MB
PCI Target 32-bit/33MHz
FPGA-RD-021343.61/31/2021PDF1.8 MB
PCI/WISHBONE Bridge
FPGA-RD-021351.42/5/2021PDF1.2 MB
RGMII to GMII Bridge - Source Code
7/15/2025ZIP382.7 KB
RGMII to GMII Bridge Reference Design - User Guide
FPGA-RD-021362.67/15/2025PDF257.7 KB
WISHBONE UART - Documentation
FPGA-RD-021371.72/5/2021PDF1.1 MB
WISHBONE UART - Source Code
RD10421.612/1/2014ZIP58.5 MB
标题编号版本日期格式文件大小
选择全部
ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-1114/1/2011PDF796.6 KB
Courtesy Notification of Additional Ejector Pin Sites on Select BGA Packages
5/22/2013PDF252.9 KB
PCN 02A-16 ECP5/ECP5-5G updates on Diamond v3.7
PCN02A-161.03/1/2016PDF162.6 KB
PCN 03C13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set
PCN03C1.011/14/2014PDF212.8 KB
PCN 09A-12 Affected Devices
Assembly Site
PCN09A-121.05/14/2012XLSX121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-121.05/14/2012PDF160.2 KB
PCN 09A-12 Customer Characterization Report
PCN09A-121.05/14/2012PDF551.7 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-121.05/11/2012PDF178.9 KB
PCN 09A-12 Material Set Changes
Assembly Site
PCN09A-121.05/14/2012XLSX121 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-136/28/2013PDF202.5 KB
PCN03A-13 Device Characterization Report
PCN03A-136/28/2013PDF981.3 KB
PCN03A-13 FAQs
PCN03A-136/28/2013PDF458.3 KB
PCN03A-14 Characterization Report
PCN03A-141.04/4/2014PDF919.5 KB
PCN03A-14 FAQ
PCN03A-141.04/4/2014PDF452.5 KB
PCN03A-14 Material Set Table
PCN03A-141.04/4/2014XLSX26.9 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-141.011/21/2014PDF229.9 KB
PCN03C-13 Affected Part Number and Material Sets
PCN03C-136/28/2013XLSX51.2 KB
PCN03C-14 Affected Part Number List
PCN03C-141.04/4/2014XLSX50.8 KB
PCN05A-11 Notification of Intent to Utilize an Alternate Foundry Process for LatticeECP3
Process
PCN05A-111.04/11/2011PDF207.6 KB
PCN05A-17 Affected Parts List
1.010/18/2017XLSX14.9 KB
PCN05A-17 Halogen-Free substrate at ASEM
1.210/27/2017PDF268 KB
PCN06A-14 Characterization Report
PCN06A-141.010/3/2014PDF563.7 KB
PCN06A-14 Material Set Table
PCN06A-141.010/3/2014XLSX13.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-141.011/21/2014PDF229.5 KB
PCN06C-14 Affected Device List
PCN06C-141.010/3/2014XLSX29.6 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set
PCN07C-111.08/1/2011PDF917.9 KB
PCN08A13_AffectedDevices
Other
PCN08A-1319/26/2013XLSX78.2 KB
PCN10A-11 Notification of Intent to Freeze ispLEVER After Version 8.2
Conversion
PCN10A-111.07/25/2011PDF52.7 KB
PCN11A-10 Notification of Change of Ordering Part Number for the LFE3-70E and LFE3-95E to the LFE3-70EA and LFE3-95EA, Respectively
PCN11A-1017/9/2010PDF59 KB
PCN11A-10 Notification of Change of Ordering Part Number for the LFE3-70E and LFE3-95E to the LFE3-70EA and LFE3-95EA, Respectively - Japanese Language
PCN11A-1017/9/2010PDF144.1 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.16/26/2026ZIP3.3 MB
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Automotive Solutions Product Brief
I01648.07/2/2013PDF2.5 MB
Automotive Solutions Product Brief (Chinese)
I0164hc8.08/7/2013PDF2.5 MB
Ethernet Solutions Brochure
I01942.012/16/2009PDF2 MB
IP Suites for LatticeECP3 - News Brief
NB1012/4/2011PDF458.8 KB
Lattice HetNet Solutions Brochure
I02341.011/12/2013PDF2.2 MB
LatticeECP3 Family Product Brochure
I01988.05/29/2012PDF2.7 MB
LatticeECP3 Product Brief (Chinese)
I0198C7.05/29/2012PDF3.1 MB
LatticeECP3 Versa Development Kit - News Brief
NB1032.07/5/2012PDF364.2 KB
LatticeECP3: First PCIe 2.0 Compliant Low Cost FPGA - News Brief
NB1047/1/2011PDF479.5 KB
New LatticeECP3 Devices - News Brief
NB1061.01/23/2012PDF343.5 KB
SERCOS III Evaluation Kit Product Brief
I02231.02/24/2012PDF772.8 KB
Wireless Solutions Brochure
I01973.08/14/2012PDF2 MB
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FN1156_FE3
Rev K26/8/2022PDF150.7 KB
FN484
Rev K16/8/2022PDF30.4 KB
FN484_LAE3
Rev G16/8/2022PDF142.2 KB
FN672
Rev L16/8/2022PDF154.1 KB
FN672_LAE3
Rev H16/8/2022PDF141.3 KB
FTN256_v2_FE3
Rev Q16/9/2022PDF154 KB
MG328_FE3
Rev S16/21/2022PDF148 KB
MG328_LAE3
Rev Q16/21/2022PDF142.1 KB
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LatticeECP3 PCI Express Development Kit Installation Read Me - Linux
3/9/2011TXT0.2 KB
LatticeECP3 PCI Express Development Kit Installation Read Me - Windows
3/9/2011TXT0.2 KB
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Designing for Low Power (LatticeECP3)
1.03/10/2010PDF140.2 KB
Embedded Display Control Using FPGAs (Chinese Language)
1.06/28/2010PDF1.5 MB
Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block
1.02/19/2009PDF195.9 KB
Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block (Chinese Language)
1.06/8/2009PDF457.9 KB
Expanding Microprocessor Connectivity Using Low-cost FPGAs (Chinese)
1.08/28/2013PDF660.7 KB
FPGAs in Next Generation Wireless Networks (Chinese Language)
5/22/2013PDF3.5 MB
FPGAs in Next Generation Wireless Networks (Japanese Language)
1.03/10/2010PDF284.1 KB
FPGAs in Next Generation Wireless Networks (Korean Language)
5/22/2013PDF3.9 MB
FPGAs in Next Generation Wireless Networks (LatticeECP3)
1.03/10/2010PDF174.7 KB
FPGAs in Next Generation Wireless Networks (Traditional Chinese Language)
1.05/22/2013PDF1.5 MB
Gen2 Serial RapidIO and Low Cost Low Power FPGAs (Korean Language)
1.09/26/2011PDF349 KB
GEN2 Serial RapidIO and Low Cost, Low Power FPGAs
1.08/4/2011PDF276 KB
GEN2 Serial RapidIO and Low Cost, Low Power FPGAs - Chinese Language
1.05/22/2013220.2 KB
High-Speed SERDES Interfaces In High Value FPGAs (LatticeECP3)
1.02/19/2009PDF503 KB
Implementing DDR3 Memory Controller (LatticeECP3)
1.03/10/2010PDF147.9 KB
Implementing PCI Express Bridging Solutions in an FPGA
1.07/1/2010PDF970.1 KB
Implementing PCI Express Bridging Solutions in an FPGA (Chinese Language)
1.07/1/2010PDF1007.1 KB
Power Considerations in FPGA Design (Chinese Language)
1.06/8/2009PDF814.7 KB
Power Considerations in FPGA Design (LatticeECP3)
1.02/19/2009PDF282.1 KB
Power WP - Design Example Source Code (LatticeECP3)
1.02/17/2009ZIP1.4 KB
在嵌入式设计中采用基于D-PHY的MIPI标准外设
1.05/1/2014PDF495.9 KB
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[BSDL] LFE3-150EA FPBGA1156
1.019/10/2012BSM125.8 KB
[BSDL] LFE3-150EA FPBGA672
1.019/10/2012BSM97.9 KB
[BSDL] LFE3-17EA CSBGA328
1.012/14/2014BSM41.3 KB
[BSDL] LFE3-17EA FPBGA256
1.022/14/2014BSM40.8 KB
[BSDL] LFE3-17EA FPBGA484
1.022/12/2014BSM52.2 KB
[BSDL] LFE3-35EA FPBGA256
1.019/10/2012BSM47.9 KB
[BSDL] LFE3-35EA FPBGA484
1.022/7/2014BSM63.6 KB
[BSDL] LFE3-35EA FPBGA672
1.019/10/2012BSM69.5 KB
[BSDL] LFE3-70E FPBGA1156
1.039/10/2012BSM110.2 KB
[BSDL] LFE3-70E FPBGA484
1.029/10/2012BSM77.7 KB
[BSDL] LFE3-70E FPBGA672
1.029/10/2012BSM89.1 KB
[BSDL] LFE3-70EA FPBGA1156
1.019/10/2012BSM109.9 KB
[BSDL] LFE3-70EA FPBGA484
1.019/10/2012BSM77.5 KB
[BSDL] LFE3-70EA FPBGA672
1.019/10/2012BSM88.9 KB
[BSDL] LFE3-95E FPBGA1156
1.029/10/2012BSM110.1 KB
[BSDL] LFE3-95E FPBGA484
1.039/10/2012BSM77.8 KB
[BSDL] LFE3-95E FPBGA672
1.039/10/2012BSM89.2 KB
[BSDL] LFE3-95EA FPBGA1156
1.019/10/2012BSM109.9 KB
[BSDL] LFE3-95EA FPBGA484
1.019/10/2012BSM77.5 KB
[BSDL] LFE3-95EA FPBGA672
1.019/10/2012BSM88.9 KB
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ECP3 Device Family DELPHI Models
1.03/20/2009ZIP247.2 KB
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[IBIS] Lattice ECP3
2.29/10/2012IBS64.3 MB
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LatticeECP3 Versa Kit - SerDes Eye Backplane Demo - Design Files for Linux
Demonstrates the SERDES performance of the LatticeECP3 FPGA at 3.125Gbps using the LatticeECP3 Versa board, along with Lattice software. Installation includes documentation and source files.
01.05/22/2013GZ2.7 MB
LatticeECP3 Versa Kit - SerDes Eye Backplane Demo - Design Files for Windows
Demonstrates the SERDES performance of the LatticeECP3 FPGA at 3.125Gbps using the LatticeECP3 Versa board, along with Lattice software. Installation includes documentation and source files.
1.05/22/2013EXE4.8 MB
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DDR2 Demo for the LatticeECP3 Serial Protocol Board - demo files
Demo source files for the DDR2 Demo, for use with the LatticeECP3 Serial Protocol Board
5/22/2013ZIP582.7 KB
ECP3 PCI Express Development Kit Demos (Linux)
5/22/2013GZ56.2 MB
ECP3 PCI Express Development Kit Demos (Windows)
5/22/2013EXE48.5 MB
LatticeECP3 CPRI Demo Design
2.05/3/2012ZIP7.2 MB
LatticeECP3 DDR3 Demo
1.46/8/2012ZIP235.3 KB
LatticeECP3 PCI Express Root Complex Lite x1 Native Demo
1.011/1/2010ZIP2.7 MB
LatticeECP3 SERDES Eye/Backplane Demo Design
1.18/4/2010ZIP874.3 KB
LatticeECP3 XAUI Demo
1.36/16/2011ZIP1.8 MB
Tri-Rate SMPTE SDI Demo
For use with ispLEVER 8.1 SP1
2.04/24/2014ZIP1.5 MB
Tri-Rate SMPTE SDI Demo
For use with ispLEVER 7.2 SP2
1.04/30/2009ZIP1.5 MB

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