This solution is an FPGA bitstream that can be used to configure a Lattice FPGA to perform as a Single-Wire aggregator for I2C, I2S, and GPIO signalling. No FPGA design is needed. Two configured devices (denoted as Master Single-Wire Aggregation Device and Slave Single-Wire Aggregation Device) can be used to aggregate and deaggregate multiple signals on a single physical wire through Time Domain Multiplexing (TDM)-based bidirectional communication.
Note: UART can be implemented using GPIO channel.
Single Wire Signal Aggregation Demonstration – Two boards are provided to demonstrate the complete working design in a stand-alone configuration.
Features
- No FPGA tools knowledge necessary
- Customizable via available Reference Design
- Up to 7 channels can be aggregated
- Supports ultra-low power devices
- Multiple sets of ready-to-use configurations to support different use case applications are available
