QDR SRAM Memory Controller

QDR SRAM is a new memory technology defined by a number of leading memory venders for high-performance and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate unidirectional data buses dedicated for read and write operations running at double data rate. This reference design utilizes the ORCA Series 4 library elements IODDR and HIODDR to create 178MHz double data rate read/write access to the QDR memory and targets for ORCA 4 FPGA and FPSC devices.

Support Discontinued - For Reference Only

Block Diagram

Performance and Size

Family	Tested Devices*	PLL Usage	PFU Usage(include pipeline module)	Registers Usage	Max. Freq.
ORCA4 FPSC	ORSPI4-2FE1036C	2	75 out of 2024	643(includes 360 registers for pipeline module)	178 MHz
LatticeEC	LFEC20E-4F672C	2	75 out of 2464	613(includes 360 registers for pipeline module)	192 MHz
LatticeXP	LFX10C-4f388C	2	71 out of 1216	612 (includes 360 registers for pipeline module)	178 MHz

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources

Reference Design

TITLE	NUMBER	DATE	FORMAT	SIZE
Select All
QDR Memory Controller - Documentation	RD1019	5/3/2005	ZIP	2.6 MB
QDR Memory Controller - Source Code	RD1019	5/3/2005	ZIP	2.6 MB

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