This reference design is intended to read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash with non-volatile FPGA/CPLD devices. It provides a way to fetch design or manufacturing information without interrupting the normal operation of the system. UES is supported by Lattice devices such as MachXO and LatticeXP2 to store simple data for identification purposes. It provides a small “writing pad” for engineering and manufacturing to manage revision control in silicon. The Usercode can be defined during the design stage or the programming stage. During power up, Usercode is programmed into SRAM along with the design.
Support Discontinued - For Reference Only








