Certus-N2

High Performance General Purpose Small FPGA

Related Applications

The Lattice Certus-N2 family of small, general purpose FPGAs deliver up to 220k System Logic Cells of density and up to 8 – 16G multi-protocol SerDes and offer small package options. Built using the Lattice Nexus 2 platform – the family is optimized for low power relative to the competition and supports industry-leading design security in its class.

Improved Performance – 2X more logic density, SerDes speed, and DSP to logic ratio than previous generation

Fast External Memory Support – LPDDR4/DDR4 up to 2400 Mbps

Low Power – Up to 3x lower power than competitive products

Features

  • Up to 8 SerDes channels operating up to 128 Gbps total bandwidth
  • Packages as small as 9x9 mm2 with SerDes, and in ball-pitch options of 0.5, 0.8, and 1.0 mm
  • FPGA fabric features up to 220k System Logic Cells, 12 Mb embedded memory, and 520 – 18 x 18 multipliers
  • Instant-on: < 20 ms configuration using xSPI flash memory
  • Class leading bitstream encryption and authentication

Jump to

Family Table

Certus-N2 Device Selection Guide
Features CT06 CT10 CT16 CT20
System Logic Cells (k) 65 100 160 220
Look-Up-Tables (k LUTs) 40 61 98 135
Embedded Memory (EBR) Blocks (36 kb) 114 153 228 306
Embedded Memory (Mb) 4 5.5 8 12
Distributed RAM Bits (kb) 416 636 1041 1272
DSP (18x18 Multipliers) 120 240 360 520
High Frequency Oscillator (400 MHz) 1 1 1 1
GPLL 4 4 7 7
External Memory Interface support LPDDR4/DDR4
Max 16G SerDes Channels 4 4 8 8
Temperature Grades1 C, I C, I C, I C, I
Bitstream Encryption / Authentication AES-GCM / ECDSA / RSA
0.5 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
ASG273 (FOWLP, 9 × 9 mm, 0.5 mm) 112 (27, 85) / 4 112 (27, 85) / 4
ASG410 (FOWLP, 11 × 9 mm, 0.5 mm) 247 (94,153) 247 (94,153)
196 (43, 153) / 4 196 (43, 153) / 4
0.8 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
CBG256 (FCCSP , 14 × 14 mm, 0.8 mm) 153 (51, 102) / 2 153 (51, 102) / 2
CBGG484 (FCCSP, 18 × 18 mm, 0.8 mm) 196 (94, 102) / 4 196 (94, 102) / 4 247(94,153) / 4 247(94,153) / 4
1.0 mm Total I/O (Wide Range / High Performance) / SerDes

CT06 CT10 CT16 CT20
LFG676 (FCBGA, 27 × 27 mm, 1.0 mm) 298 (43, 255) / 8 298 (43, 255) / 8

1. C=Commercial, I=Industrial

Example Solutions

Industrial Machine Vision

  • Sensor Interface - MIPI CSI-2, LVDS, SubLVDS
  • Customizable ISP for image processing
  • High BW 10GbE connectivity for streaming lossless quality video

Automotive Zonal Controller / Gateway

  • Interface bridging and low latency switching
  • Flexible Ethernet, sensor / actuator port configuration
  • Optional image data compression to optimize bandwidth and reduce latency

Frame Grabber

  • Image acquisition, pre-processing, compression (optional) and DMA over PCIe to host PC
  • SerDes supporting 10GbE video in and PCIe out
  • LPDDR4 external memory support for optional frame buffering

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-021220.737/9/2026PDF1.3 MB
Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-021210.727/2/2025PDF1.4 MB
Lattice Nexus 2 Power User Guide
FPGA-TN-023810.8012/10/2024PDF352.4 KB
Lattice Nexus 2 SERDES/PCS User Guide
FPGA-TN-023950.804/15/2025PDF2.3 MB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-023640.8112/10/2024PDF1 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.16/26/2026ZIP3.3 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.35/6/2026PDF753.9 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Thermal Management
FPGA-TN-020446.08/19/2026PDF976.2 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-021220.737/9/2026PDF1.3 MB
Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-021210.727/2/2025PDF1.4 MB
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Lattice Nexus 2 Configuration Security User Guide
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-TN-023690.83/14/2025WEB
Lattice Nexus 2 Device Security User Guide
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-TN-023680.83/14/2025WEB
Lattice Nexus 2 Embedded Memory User Guide
FPGA-TN-023660.8112/10/2024PDF1.1 MB
Lattice Nexus 2 Hardware Checklist
FPGA-TN-023820.8211/5/2025PDF906.3 KB
Lattice Nexus 2 High-Speed I/O and External Memory Interface User Guide
FPGA-TN-023720.8112/10/2024PDF1.5 MB
Lattice Nexus 2 Multi-Boot User Guide
FPGA-TN-023850.8012/10/2024PDF366.5 KB
Lattice Nexus 2 Power User Guide
FPGA-TN-023810.8012/10/2024PDF352.4 KB
Lattice Nexus 2 SED/SEC User Guide
FPGA-TN-023800.8012/10/2024PDF311.3 KB
Lattice Nexus 2 SERDES/PCS User Guide
FPGA-TN-023950.804/15/2025PDF2.3 MB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-023640.8112/10/2024PDF1 MB
Lattice Nexus 2 sysCONFIG User Guide
FPGA-TN-023700.8112/10/2024PDF3.2 MB
Lattice Nexus 2 sysDSP User Guide
FPGA-TN-023620.823/17/2025PDF814 KB
Lattice Nexus 2 sysI/O User Guide
FPGA-TN-023650.8112/10/2024PDF647.8 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.35/6/2026PDF753.9 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Thermal Management
FPGA-TN-020446.08/19/2026PDF976.2 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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Certus-N2 CT20 Pinout Table
FPGA-SC-021080.803/26/2026CSV40.9 KB
Certus-N2 CT20E/16E Pinout Table
FPGA-SC-021190.707/21/2026CSV20.5 KB
Lattice Nexus 2 Package Diagram
FPGA-DS-021240.8112/10/2024ZIP105.6 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.16/26/2026ZIP3.3 MB
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Lattice FPGA Product Selector Guide
v26.1.14/6/2026PDF762.9 KB
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Lattice Nexus™ 2 Platform: Low Power, High Performance Small FPGA
WP00401.012/10/2024PDF759.9 KB
Random Bin Picking Based On Structured-Light 3D Scanning
WP00432.05/22/2025PDF3.7 MB
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Certus-N2 CT20 BSDL Model file
FPGA-MD-020840.812/10/2024ZIP19.1 KB
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Lattice Nexus 2 Delphi Models
FPGA-MD-020750.8112/5/2024ZIP17.5 KB
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[IBIS] Certus-N2
FPGA-MD-020780.811/6/2026ZIP28.7 MB