The Serial Peripheral Interface (SPI) bus provides an industry standard interface between microprocessors and other devices as shown in the block diagram below. This reference design documents a SPI WISHBONE controller designed to provide an interface between a microprocessor with a WISHBONE bus and external SPI devices. In master mode, the SPI controller can be configured for communication with multiple off-chip SPI ports. In slave mode, the SPI supports communications with an off-chip SPI master.
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Block Diagram
Performance and Size
| Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|
| LCMXO2280C-5FT256C | >70MHz | 38 | 112 LUTs (VHDL) 116 LUTs (Verilog) |
1.5 |
| LC4256ZE-5MN144C | >70MHz | 38 | 95 Macrocells (VHDL) 94 Macrocells (Verilog) |
1.5 |
| LFXP2-5E-5FT256C | >70MHz | 38 | 148 LUTs | 1.5 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Documentation
Technical Resources |
| TITLE | NUMBER | VERSION | DATE | FORMAT | SIZE | ||
|---|---|---|---|---|---|---|---|
| Select All | |||||||
| SPI WISHBONE Controller - Documentation | RD1044 | 1.7 | 3/1/2014 | 960 KB | |||
| SPI WISHBONE Controller - Source Code | RD1044 | 1.8 | 1/12/2015 | ZIP | 477.7 KB | ||
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