This reference design provides a NOR flash memory controller through WISHBONE bus. It supports several common operational modes of a NOR flash, including reset operation, autoselect manufacturer ID operation, read operation, program operation, chip erase operation and sector erase operation.
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-6TG144CES | Verilog | > 80 MHz | 80 | 185 LUTs | 1.1 |
| LCMXO2-1200HC-6TG144CES | VHDL | > 80 MHz | 80 | 190 LUTs | 1.1 |
| LCMXO1200C-3T144C | Verilog | > 80 MHz | 80 | 182 LUTs | 1.1 |
| LCMXO1200C-3T144C | VHDL | > 80 MHz | 80 | 187 LUTs | 1.1 |
1 The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Technical Resources |
| TITLE | NUMBER | VERSION | DATE | FORMAT | SIZE | ||
|---|---|---|---|---|---|---|---|
| Select All | |||||||
| NOR Flash Memory Controller with WISHBONE Interface - Documentation | FPGA-RD-02096 | 1.2 | 1/22/2021 | 1.6 MB | |||
| NOR Flash Memory Controller with WISHBONE Interface - Source Code | RD1087 | 1.1 | 11/8/2010 | ZIP | 198.1 KB | ||
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