This reference design describes how to set up and run the Mixed Mode PCI Express (PCIe) basic demo and Tri-Speed Ethernet (TSE) in loopback mode using devices built on the CertusPro™-NX FPGA.
The demo is targeted for CertusPro-NX Versa Evaluation Board, which features the CertusPro-NX FPGA in the LFG672 package. The above-mentioned FPGAs are built on the Nexus™ FPGA platform using low-power 28 nm FD-SOI technology.
Features
- Read and write to onboard memory of the CertusPro-NX FPGA through PCIe
- Three 7-segment LED control using Lattice Nexus FPGA through PCIe Interface
- Packet generator and checker implemented through TSEMAC through external loopback
