LatticeECP3 Video Protocol Board

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No longer available - for reference only. Includes video interfaces for ECP3 FPGA to various video standards + SD/HD/3G-SDI, DisplayPort, 7:1 LVDS video

The LatticeECP3 FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented with 16 channels of embedded SERDES/ PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also be used to receive the TMDS signals of DVI or HDMI video standard. PCB Revision Notes Starting in March 2010, Lattice will be shipping Revision C LatticeECP3 Video Protocol boards. This revision includes some minor changes which are summarized below, and detailed in the Revision C User's Guide. Pull-up resistors added to the DVI Rx and DDR2 DQS signals Provision for resistor between the P and N reference clocks of SERDES Quad C Gennum clock generators (GS4911) on U2 and U3 are not populated, as this feature is not used in any of the standard evaluation modes. Demos 7:1 LVDS Reference Design

LFE3-95EA-V-EVN, Lattice ECP3 video protocol board

Kits, Boards & Cables

LatticeECP3

Boards

PCIe

SDI Video

Lattice

69900

LatticeECP3 Video Protocol Board

The LatticeECP3™ FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented with 16 channels of embedded SERDES/ PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also be used to receive the TMDS signals of DVI or HDMI video standard.

PCB Revision Notes

Starting in March 2010, Lattice will be shipping Revision C LatticeECP3 Video Protocol boards. This revision includes some minor changes which are summarized below, and detailed in the Revision C User's Guide.

Pull-up resistors added to the DVI Rx and DDR2 DQS signals
Provision for resistor between the P and N reference clocks of SERDES Quad C
Gennum clock generators (GS4911) on U2 and U3 are not populated, as this feature is not used in any of the standard evaluation modes.

Demos

7:1 LVDS Reference Design

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Features

Video interfaces for interconnection to video standard equipment
Allow the demonstration of SD/HD/3G-SDI, DisplayPort and PCI Express (x4) interfaces using SERDES channels
High speed Mezzanine connector connected to SERDES channels for future expansion
Allows the demonstration of LVDS video standards – ChannelLink and CameraLink
Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
Allows the demonstration of receiving TMDS signals using the DVI interface
On-board Boot Flash with Serial SPI Flash memory device
Shows interoperation with high performance DDR2 memory components
Driver-based “run-time” device configuration capability via an ORCAstra or RS232 interface
SMAs for external high-speed clock / PLL inputs
Switches, LEDs and LCD display header for demo purposes
Mictor connector for using Logic Analyzer in the debugging phase
Input connection for lab-power supply
Power connections and power sources
ispVM™ programming support
On-board and external reference clock sources
Various high-speed layout structures
User-defined input and output points
Performance monitoring via test headers, LEDs and switches

Board Photos

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Bottom View

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Ordering Information

Reference Number: LFE3-95EA-V-EVN
This board is no longer available for purchase.
Information provided on this page is for reference purposes only.
Contact your local Lattice sales representative for further information.

Documentation

Quick Reference

Information Resources

Downloads

Downloadable Software

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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Parallel Flash Programming and FPGA Configuration - Source Code For use with Application Note - AN8077	AN8077	1.3	1/4/2013	RAR	1.4 MB

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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Parallel Flash Programming and FPGA Configuration - Source Code For use with Application Note - AN8077	AN8077	1.3	1/4/2013	RAR	1.4 MB

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TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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HDMI Mezzanine Card User's Guide	EB55	1.1	9/24/2012	PDF	1.9 MB
HDMI/DVI Loopback Demo User's Guide	UG36	1.0	5/22/2013	PDF	2.2 MB
LatticeECP3 Video Protocol Board - Revision B User's Guide	EB39	1.3	3/2/2010	PDF	2.5 MB
LatticeECP3 Video Protocol Board - Revision C - User's Guide	EB52	01.3	10/4/2012	PDF	4.8 MB
Programming Cable - User Guide Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables.	FPGA-UG-02042	26.7	4/24/2024	PDF	992.6 KB

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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Lattice HetNet Solutions Brochure	I0234	1.0	11/12/2013	PDF	2.2 MB
Wireless Solutions Brochure	I0197	3.0	8/14/2012	PDF	2 MB

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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GEN2 Serial RapidIO and Low Cost, Low Power FPGAs		1.0	8/4/2011	PDF	276 KB
GEN2 Serial RapidIO and Low Cost, Low Power FPGAs - Chinese Language		1.0	5/22/2013		220.2 KB
Implementing PCI Express Bridging Solutions in an FPGA		1.0	7/1/2010	PDF	970.1 KB
Implementing PCI Express Bridging Solutions in an FPGA (Chinese Language)		1.0	7/1/2010	PDF	1007.1 KB

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
Select All
Tri-Rate SMPTE SDI Demo For use with ispLEVER 8.1 SP1		2.0	4/24/2014	ZIP	1.5 MB
Tri-Rate SMPTE SDI Demo For use with ispLEVER 7.2 SP2		1.0	4/30/2009	ZIP	1.5 MB