Industry standard interface - The Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices. This reference design is designed to provide an interface between a generic processor with parallel bus interface and external SPI devices.
Compatible with all SPI Modes - SPI interface is a good choice for designs that require full-duplex capability for sending and receiving data at the same time. The SPI Master Controller can communicate with multiple off-chip SPI ports and can also be configured to support all modes of CPOL and CPHA (00, 01, 10, and 11).
Complete Reference Design and Demo - Training dataset, project & source files, demo files and test bench are provided to enable modification.
Features
- Supports a wide array of Lattice FPGAs such as MachXO2™, MachXO3™, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
- Provision for easy integration of any processor interface
- Up to five slave select outputs
- Configurable timing features for timing-sensitive slave devices
