PAC-Designer 设计软件

高效率的设计软件——适用于电源和时钟管理的设计工具

相关产品

完美适配——PAC-Designer为采用Power Manager和Platform Manager器件的设计开发量身定制。

从设计开始到最终完成——PAC-Designer 是适用于Power Manager和Platform Manager器件的一款完备的设计实现和验证工具。

能很好地与别的工具相配合——能与Lattice Diamond软件无缝衔接，助您开发创新的混合信号解决方案。

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概述

莱迪思针对集成的电源、平台和时钟管理器件建立了行业标准，而PAC-Designer设计软件正是在您的设计上发挥出以上解决方案最大潜力的关键。

提升至更高效的环境

  • 完全集成的设计和仿真环境，适用于Platform Manager、Power Manager II和ispClock器件
  • 高层次的逻辑设计机制
  • 易于使用的图形用户界面
  • Platform Manager, PAC-Designer与ispLEVER软件相结合，形成一个完整的CPLD/ FPGA设计环境

值得信任，但仍需验证

  • 导出VHDL或Verilog HDL模型到常用的第三方HDL仿真器
  • 构建图形化的电源管理激励
  • 数字波形仿真，便于设计验证
  • 模拟电源范围

轻松编程

  • 使用Diamond Programmer（包含在Lattice Diamond内）将您的设计下载至Platform Manager器件
  • 针对Platform Manager以外的产品，可使用PAC-Designer对Platform Manager、Power Manager II和ispClock器件直接进行编程

许可证

PAC-Designer 许可证 （仅用于PAC-Designer5.1或更早的版本）

申请一个许可证您需要：

  • 莱迪思网站的用户帐户
  • 硬盘序列号

点击此处申请您的许可证。

文档

快速参考
技术资源
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标题编号版本日期格式文件大小
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Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
标题编号版本日期格式文件大小
选择全部
Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
标题编号版本日期格式文件大小
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PAC-Designer Installation Notice 6.32
6.322/22/2016PDF387.3 KB
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PAC-Designer Software User Manual 6.32
1.06/1/2014PDF3.3 MB
Platform Designer 3.11 User Guide
1.06/1/2019PDF697.9 KB
Platform Management Utility Functions IP Core User's Guide
IPUG9401.11/24/2011PDF551.8 KB
Platform Manager Development Kit User's Guide
EB5801.212/7/2010PDF1.6 MB
Power Manager II Hercules Development Kit User's Guide
EB5701.012/22/2010PDF3 MB
标题编号版本日期格式文件大小
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BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
Closed Loop Power Supply Trimming Documentation
RD10781.012/6/2010PDF278.2 KB
Closed Loop Power Supply Trimming Source Code
RD10781.012/6/2010ZIP269.4 KB
Error Logging Using Platform Manager Documentation
RD10771.09/28/2010PDF422.5 KB
Error Logging Using Platform Manager Source Files
RD10771.09/28/2010ZIP372.9 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
Hercules Development Kit Demonstration Source Code
1.06/11/2010ZIP201.6 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
Long Delay Timers Using Platform Manager Documentation
RD10791.19/28/2010PDF874.1 KB
Long Delay Timers Using Platform Manager Source Files
RD10791.09/28/2010ZIP683.9 KB
Platform Manager Dev Kit Initial Demo Source Files
RD1.11/26/2011ZIP1.1 MB
Power Management Bus Reference Design - Source Code
RD11001.112/23/2011ZIP378.3 KB
Power Management Bus Reference Design Documentation
FPGA-RD-020971.21/22/2021PDF1.1 MB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
PWM Fan Controller - Source Code
RD10601.71/16/2015ZIP2.9 MB
Temperature Monitor Using Platform Manager Documentation
RD10801.09/28/2010PDF330 KB
Temperature Monitor Using Platform Manager Source Files
RD10801.09/28/2010ZIP256.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
7/15/2025ZIP772.5 KB
UART (Universal Asynchronous Receiver/Transmitter) - User Guide
FPGA-RD-022701.87/15/2025PDF741.9 KB
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Platform Manager Product Brochure
I02081.04/10/2012PDF2.8 MB
Platform Manager Product Brochure (Chinese)
I0208C1.06/4/2012PDF2.9 MB
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Software Cable Support
2.07/16/2012PDF194.8 KB
标题编号版本日期格式文件大小
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PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device.		PDT0101.18/15/2008PDF1.3 MB
标题编号版本日期格式文件大小
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LPTM10_12107_XO640
1.0110/8/2014BSM30.3 KB
LPTM10_1247_MO640
1.0110/8/2014BSM24.9 KB
Platform Manager 128 TQFP BSDL Files
1.12/26/2013ZIP8.4 KB
Platform Manager 208 ftBGA BSDL Files
1.12/27/2014ZIP10 KB
标题编号版本日期格式文件大小
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PAC Designer 6.30 for Windows
6.329/26/2023ZIP120.1 MB
Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.13/19/2012ZIP63.1 KB